verilog编写的1024点的fft快速傅立叶变换代码全解Word文档格式.docx

verilog编写的1024点的fft快速傅立叶变换代码全解Word文档格式.docx

《verilog编写的1024点的fft快速傅立叶变换代码全解Word文档格式.docx》由会员分享，可在线阅读，更多相关《verilog编写的1024点的fft快速傅立叶变换代码全解Word文档格式.docx（94页珍藏版）》请在冰豆网上搜索。

0]s3_3;

wires4_1;

0]s4_2;

0]s4_3;

cf_fft_1024_8_23s1（clock_c,s3_1,s3_2,s3_3,i4,i5,s1_1,s1_2,s1_3）;

cf_fft_1024_8_6s2（clock_c,s1_1,s1_2,s1_3,i4,i5,s2_1,s2_2,s2_3）;

cf_fft_1024_8_5s3（clock_c,s4_1,s4_2,s4_3,i4,i5,s3_1,s3_2,s3_3）;

cf_fft_1024_8_2s4（clock_c,i1,i2,i3,i4,i5,s4_1,s4_2,s4_3）;

assigno3=s2_3;

assigno2=s2_2;

assigno1=s2_1;

modulecf_fft_1024_8_2（clock_c,i1,i2,i3,i4,i5,o1,o2,o3）;

wire[31:

0]n1;

wiren2;

wiren3;

wire[7:

0]n4;

0]n5;

wire[1:

0]n6;

0]n7;

0]n8;

0]n9;

0]n10;

0]n11;

0]n12;

wires13_1;

0]s14_1;

wires15_1;

wires15_2;

0]s15_3;

wire[8:

0]s16_1;

wires16_2;

assignn1={i2,i3};

assignn2=s16_1[8];

assignn3=~n2;

assignn4={s16_1[7],

s16_1[6],

s16_1[5],

s16_1[4],

s16_1[3],

s16_1[2],

s16_1[1],

s16_1[0]};

assignn5={n4[0],

n4[1],

n4[2],

n4[3],

n4[4],

n4[5],

n4[6],

n4[7]};

assignn6={s15_2,s15_1};

assignn7={s15_3[31],

s15_3[30],

s15_3[29],

s15_3[28],

s15_3[27],

s15_3[26],

s15_3[25],

s15_3[24],

s15_3[23],

s15_3[22],

s15_3[21],

s15_3[20],

s15_3[19],

s15_3[18],

s15_3[17],

s15_3[16]};

assignn8={s15_3[15],

s15_3[14],

s15_3[13],

s15_3[12],

s15_3[11],

s15_3[10],

s15_3[9],

s15_3[8],

s15_3[7],

s15_3[6],

s15_3[5],

s15_3[4],

s15_3[3],

s15_3[2],

s15_3[1],

s15_3[0]};

assignn9={s14_1[31],

s14_1[30],

s14_1[29],

s14_1[28],

s14_1[27],

s14_1[26],

s14_1[25],

s14_1[24],

s14_1[23],

s14_1[22],

s14_1[21],

s14_1[20],

s14_1[19],

s14_1[18],

s14_1[17],

s14_1[16]};

assignn10={s14_1[15],

s14_1[14],

s14_1[13],

s14_1[12],

s14_1[11],

s14_1[10],

s14_1[9],

s14_1[8],

s14_1[7],

s14_1[6],

s14_1[5],

s14_1[4],

s14_1[3],

s14_1[2],

s14_1[1],

s14_1[0]};

assignn11=s13_1?

n8:

n7;

assignn12=s13_1?

n10:

n9;

cf_fft_1024_8_33s13（clock_c,n6,i4,i5,s13_1）;

cf_fft_1024_8_4s14（clock_c,s16_2,n1,n2,n5,i4,i5,s14_1）;

cf_fft_1024_8_3s15（clock_c,s16_2,n1,n3,n5,i4,i5,s15_1,s15_2,s15_3）;

cf_fft_1024_8_24s16（clock_c,i1,i4,i5,s16_1,s16_2）;

assigno3=n12;

assigno2=n11;

assigno1=s15_1;

modulecf_fft_1024_8_3（clock_c,i1,i2,i3,i4,i5,i6,o1,o2,o3）;

input[31:

inputi3;

input[7:

0]i4;

inputi6;

outputo2;

output[31:

wire

[7:

reg

n4;

n5;

n7;

n8;

[31:

0]n9a;

0]n9m[255:

0];

n10;

0]n11a;

0]n11m[255:

n12;

0]n13;

n14;

s15_1;

assignn1=8'

b00000001;

assignn2=n3+n1;

initialn3=8'

b00000000;

always@（posedgeclock_c）

if（n14==1'

b1）

n3<

=8'

elseif（i5==1'

=n2;

assignn4=~s15_1;

initialn5=1'

b0;

if（i6==1'

n5<

=1'

=i1;

assignn6=8'

assignn7=n3==n6;

assignn8=i3&

n4;

initialn9a=8'

if（i5==1'

b1）begin

if（n8==1'

n9m[i4]<

=i2;

n9a<

=n3;

end

assignn9=n9m[n9a];

assignn10=i3&

s15_1;

initialn11a=8'

if（n10==1'

n11m[i4]<

n11a<

assignn11=n11m[n11a];

initialn12=1'

n12<

=n4;

assignn13=n12?

n11:

assignn14=i1|i6;

cf_fft_1024_8_30s15（clock_c,i1,i5,i6,s15_1）;

assigno3=n13;

assigno2=n7;

assigno1=n5;

modulecf_fft_1024_8_4（clock_c,i1,i2,i3,i4,i5,i6,o1）;

0]o1;

reg[7:

wiren4;

wiren5;

0]n6a;

reg[31:

0]n6m[255:

wiren7;

0]n8a;

0]n8m[255:

regn9;

wiren11;

wires12_1;

if（n11==1'

assignn4=~s12_1;

assignn5=i3&

initialn6a=8'

if（n5==1'

n6m[i4]<

n6a<

assignn6=n6m[n6a];

assignn7=i3&

s12_1;

initialn8a=8'

if（n7==1'

n8m[i4]<

n8a<

assignn8=n8m[n8a];

initialn9=1'

n9<

assignn10=n9?

n6;

assignn11=i1|i6;

cf_fft_1024_8_30s12（clock_c,i1,i5,i6,s12_1）;

assigno1=n10;

modulecf_fft_1024_8_5（clock_c,i1,i2,i3,i4,i5,o1,o2,o3）;

n1;

n3;

n6;

regn13;

regn14;

regn15;

regn16;

wiren17;

0]n18;

0]n19;

0]n20;

0]n21;

0]n22;

0]n23;

0]n24;

0]s25_1;

0]s25_2;

wires26_1;

0]s27_1;

wires28_1;

wires28_2;

0]s28_3;

0]s29_1;

wires29_2;

assignn1=1'

assignn2={s25_1,s25_2};

initialn3=1'

elseif（i4==1'

=s29_2;

initialn4=1'

n4<

initialn6=1'

n6<

=n5;

assignn7={s29_1[8],

s29_1[7],

s29_1[6],

s29_1[5],

s29_1[4],

s29_1[3],

s29_1[2],

s29_1[1]};

initialn8=8'

n8<

=n7;

initialn9=8'

=n8;

initialn10=8'

n10<

=n9;

initialn11=8'

n11<

=n10;

assignn12=s29_1[0];

initialn13=1'

n13<

=n12;

initialn14=1'

n14<

=n13;

initialn15=1'

n15<

=n14;

initialn16=1'

n16<

=n15;

assignn17=~n16;

assignn18={s28_2,s28_1};

assignn19={s28_3[31],

s28_3[30],

s28_3[29],

s28_3[28],

s28_3[27],

s28_3[26],

s28_3[25],

s28_3[24],

s28_3[23],

s28_3[22],

s28_3[21],

s28_3[20],

s28_3[19],

s28_3[18],

s28_3[17],

s28_3[16]};

assignn20={s28_3[15],

s28_3[14],

s28_3[13],

s28_3[12],

s28_3[11],

s28_3[10],

s28_3[9],

s28_3[8],

s28_3[7],

s28_3[6],

s28_3[5],

s28_3[4],

s28_3[3],

s28_3[2],

s28_3[1],

s28_3[0]};

assignn21={s27_1[31],

s27_1[30],

s27_1[29],

s27_1[28],

s27_1[27],

s27_1[26],

s27_1[25],

s27_1[24],

s27_1[23],

s27_1[22],

s27_1[21],

s27_1[20],

s27_1[19],

s27_1[18],

s27_1[17],

s27_1[16]};

assignn22={s27_1[15],

s27_1[14],

s27_1[13],

s27_1[12],

s27_1[11],

s27_1[10],

s27_1[9],

s27_1[8],

s27_1[7],

s27_1[6],

s27_1[5],

s27_1[4],

s27_1[3],

s27_1[2],

s27_1[1],

s27_1[0]};

assignn23=s26_1?

n20:

n19;

assignn24=s26_1?

n22:

n21;

cf_fft_1024_8_39s25（clock_c,i2,i3,n1,i4,i5,s25_1,s25_2）;

cf_fft_1024_8_33s26（clock_c,n18,i4,i5,s26_1）;

cf_fft_1024_8_29s27（clock_c,n2,n6,n11,n16,i4,i5,s27_1）;

cf_fft_1024_8_28s28（clock_c,n2,n6,n11,n17,i4,i5,s28_1,s28_2,s28_3）;

cf_fft_1024_8_24s29（clock_c,i1,i4,i5,s29_1,s29_2）;

assigno3=n24;

assigno2=n23;

assigno1=s28_1;

modulecf_fft_1024_8_6（clock_c,i1,i2,i3,i4,i5,o1,o2,o3）;