verilog编写的1024点的fft快速傅立叶变换代码全解Word文档格式.docx

1、0 s3_3;wire s4_1;0 s4_2;0 s4_3;cf_fft_1024_8_23 s1 （clock_c, s3_1, s3_2, s3_3, i4, i5, s1_1, s1_2, s1_3）; cf_fft_1024_8_6 s2 （clock_c, s1_1, s1_2, s1_3, i4, i5, s2_1, s2_2, s2_3）; cf_fft_1024_8_5 s3 （clock_c, s4_1, s4_2, s4_3, i4, i5, s3_1, s3_2, s3_3）; cf_fft_1024_8_2 s4 （clock_c, i1, i2, i3, i4, i

2、5, s4_1, s4_2, s4_3）;assign o3 = s2_3;assign o2 = s2_2;assign o1 = s2_1;module cf_fft_1024_8_2 （clock_c, i1, i2, i3, i4, i5, o1, o2, o3）;wire 31:0 n1;wire n2;wire n3;wire 7:0 n4;0 n5;wire 1:0 n6;0 n7;0 n8;0 n9;0 n10;0 n11;0 n12;wire s13_1;0 s14_1;wire s15_1;wire s15_2;0 s15_3;wire 8:0 s16_1;wire s16

3、_2;assign n1 = i2, i3;assign n2 = s16_18;assign n3 = n2;assign n4 = s16_17,s16_16,s16_15,s16_14,s16_13,s16_12,s16_11,s16_10;assign n5 = n40,n41,n42,n43,n44,n45,n46,n47;assign n6 = s15_2, s15_1;assign n7 = s15_331,s15_330,s15_329,s15_328,s15_327,s15_326,s15_325,s15_324,s15_323,s15_322,s15_321,s15_320

4、,s15_319,s15_318,s15_317,s15_316;assign n8 = s15_315,s15_314,s15_313,s15_312,s15_311,s15_310,s15_39,s15_38,s15_37,s15_36,s15_35,s15_34,s15_33,s15_32,s15_31,s15_30;assign n9 = s14_131,s14_130,s14_129,s14_128,s14_127,s14_126,s14_125,s14_124,s14_123,s14_122,s14_121,s14_120,s14_119,s14_118,s14_117,s14_1

5、16;assign n10 = s14_115,s14_114,s14_113,s14_112,s14_111,s14_110,s14_19,s14_18,s14_17,s14_16,s14_15,s14_14,s14_13,s14_12,s14_11,s14_10;assign n11 = s13_1 ? n8 : n7;assign n12 = s13_1 ? n10 : n9;cf_fft_1024_8_33 s13 （clock_c, n6, i4, i5, s13_1）;cf_fft_1024_8_4 s14 （clock_c, s16_2, n1, n2, n5, i4, i5,

6、s14_1）;cf_fft_1024_8_3 s15 （clock_c, s16_2, n1, n3, n5, i4, i5, s15_1, s15_2, s15_3）; cf_fft_1024_8_24 s16 （clock_c, i1, i4, i5, s16_1, s16_2）;assign o3 = n12;assign o2 = n11;assign o1 = s15_1;module cf_fft_1024_8_3 （clock_c, i1, i2, i3, i4, i5, i6, o1, o2, o3）;input 31:input i3;input 7:0 i4;input i

7、6;output o2;output 31:wire7:regn4;n5;n7;n8;31:0 n9a;0 n9m 255:0;n10;0 n11a;0 n11m 255:n12;0 n13;n14;s15_1;assign n1 = 8b00000001;assign n2 = n3 + n1;initial n3 = 8b00000000;always （posedge clock_c）if （n14 = 1b1）n3 = 8else if （i5 = 1= n2;assign n4 = s15_1;initial n5 = 1b0;if （i6 = 1n5 = 1= i1;assign

8、n6 = 8assign n7 = n3 = n6;assign n8 = i3 & n4;initial n9a = 8if （i5 = 1b1） beginif （n8 = 1n9mi4 = i2;n9a = n3;endassign n9 = n9mn9a;assign n10 = i3 & s15_1;initial n11a = 8if （n10 = 1n11mi4 n11a assign n11 = n11mn11a;initial n12 = 1n12 = n4;assign n13 = n12 ? n11 :assign n14 = i1 | i6;cf_fft_1024_8_

9、30 s15 （clock_c, i1, i5, i6, s15_1）;assign o3 = n13;assign o2 = n7;assign o1 = n5;module cf_fft_1024_8_4 （clock_c, i1, i2, i3, i4, i5, i6, o1）;0 o1;reg 7:wire n4;wire n5;0 n6a;reg 31:0 n6m 255:wire n7;0 n8a;0 n8m 255:reg n9;wire n11;wire s12_1;if （n11 = 1assign n4 = s12_1;assign n5 = i3 &initial n6a

10、 = 8if （n5 = 1n6mi4 n6a assign n6 = n6mn6a;assign n7 = i3 & s12_1;initial n8a = 8if （n7 = 1n8mi4 n8a assign n8 = n8mn8a;initial n9 = 1n9 assign n10 = n9 ? n6;assign n11 = i1 | i6;cf_fft_1024_8_30 s12 （clock_c, i1, i5, i6, s12_1）;assign o1 = n10;module cf_fft_1024_8_5 （clock_c, i1, i2, i3, i4, i5, o1

11、, o2, o3）;n1;n3;n6;reg n13;reg n14;reg n15;reg n16;wire n17;0 n18;0 n19;0 n20;0 n21;0 n22;0 n23;0 n24;0 s25_1;0 s25_2;wire s26_1;0 s27_1;wire s28_1;wire s28_2;0 s28_3;0 s29_1;wire s29_2;assign n1 = 1assign n2 = s25_1, s25_2;initial n3 = 1else if （i4 = 1= s29_2;initial n4 = 1n4 initial n6 = 1n6 = n5;

12、assign n7 = s29_18,s29_17,s29_16,s29_15,s29_14,s29_13,s29_12,s29_11;initial n8 = 8n8 = n7;initial n9 = 8= n8;initial n10 = 8n10 = n9;initial n11 = 8n11 = n10;assign n12 = s29_10;initial n13 = 1n13 = n12;initial n14 = 1n14 = n13;initial n15 = 1n15 = n14;initial n16 = 1n16 = n15;assign n17 = n16;assig

13、n n18 = s28_2, s28_1;assign n19 = s28_331,s28_330,s28_329,s28_328,s28_327,s28_326,s28_325,s28_324,s28_323,s28_322,s28_321,s28_320,s28_319,s28_318,s28_317,s28_316;assign n20 = s28_315,s28_314,s28_313,s28_312,s28_311,s28_310,s28_39,s28_38,s28_37,s28_36,s28_35,s28_34,s28_33,s28_32,s28_31,s28_30;assign

14、n21 = s27_131,s27_130,s27_129,s27_128,s27_127,s27_126,s27_125,s27_124,s27_123,s27_122,s27_121,s27_120,s27_119,s27_118,s27_117,s27_116;assign n22 = s27_115,s27_114,s27_113,s27_112,s27_111,s27_110,s27_19,s27_18,s27_17,s27_16,s27_15,s27_14,s27_13,s27_12,s27_11,s27_10;assign n23 = s26_1 ? n20 : n19;assi

15、gn n24 = s26_1 ? n22 : n21;cf_fft_1024_8_39 s25 （clock_c, i2, i3, n1, i4, i5, s25_1, s25_2）;cf_fft_1024_8_33 s26 （clock_c, n18, i4, i5, s26_1）;cf_fft_1024_8_29 s27 （clock_c, n2, n6, n11, n16, i4, i5, s27_1）;cf_fft_1024_8_28 s28 （clock_c, n2, n6, n11, n17, i4, i5, s28_1, s28_2, s28_3）; cf_fft_1024_8_24 s29 （clock_c, i1, i4, i5, s29_1, s29_2）;assign o3 = n24;assign o2 = n23;assign o1 = s28_1;module cf_fft_1024_8_6 （clock_c, i1, i2, i3, i4, i5, o1, o2, o3）;