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8.2）Deviceutilizationsummary
8.3）PartitionResourceSummary
8.4）TimingReport
8.4.1）ClockInformation
8.4.2）AsynchronousControlSignalsInformation
8.4.3）TimingSummary
8.4.4）TimingDetails
8.4.5）CrossClockDomainsReport
=========================================================================
*SynthesisOptionsSummary*
----SourceParameters
InputFileName:
"
RAM0.prj"
IgnoreSynthesisConstraintFile:
NO
----TargetParameters
OutputFileName:
RAM0"
OutputFormat:
NGC
TargetDevice:
xc6slx45-2-fgg484
----SourceOptions
TopModuleName:
RAM0
AutomaticFSMExtraction:
YES
FSMEncodingAlgorithm:
Auto
SafeImplementation:
No
FSMStyle:
LUT
RAMExtraction:
Yes
RAMStyle:
ROMExtraction:
ShiftRegisterExtraction:
ROMStyle:
ResourceSharing:
AsynchronousToSynchronous:
ShiftRegisterMinimumSize:
2
UseDSPBlock:
AutomaticRegisterBalancing:
----TargetOptions
LUTCombining:
ReduceControlSets:
AddIOBuffers:
GlobalMaximumFanout:
100000
AddGenericClockBuffer（BUFG）:
16
RegisterDuplication:
OptimizeInstantiatedPrimitives:
UseClockEnable:
UseSynchronousSet:
UseSynchronousReset:
PackIORegistersintoIOBs:
EquivalentregisterRemoval:
----GeneralOptions
OptimizationGoal:
Speed
OptimizationEffort:
1
PowerReduction:
KeepHierarchy:
NetlistHierarchy:
As_Optimized
RTLOutput:
GlobalOptimization:
AllClockNets
ReadCores:
WriteTimingConstraints:
CrossClockAnalysis:
HierarchySeparator:
/
BusDelimiter:
<
>
CaseSpecifier:
Maintain
SliceUtilizationRatio:
100
BRAMUtilizationRatio:
DSP48UtilizationRatio:
AutoBRAMPacking:
SliceUtilizationRatioDelta:
5
----OtherOptions
CoresSearchDirectories:
{"
ipcore_dir"
}
INFO:
Xst-Part-selectindexevaluatedtooutofboundvaluemayleadtoincorrectsynthesisresults;
itisrecommendednottousetheminRTL
*HDLParsing*
ParsingVHDLfile"
F:
\MODEL\ISE\CONMEME\ipcore_dir\RAM.vhd"
intolibrarywork
Parsingentity<
RAM>
.
Parsingarchitecture<
RAM_a>
ofentity<
ram>
\MODEL\ISE\CONMEME\ipcore_dir\RAM2.vhd"
RAM2>
RAM2_a>
ram2>
\MODEL\ISE\CONMEME\ipcore_dir\RAM1.vhd"
RAM1>
RAM1_a>
ram1>
\MODEL\ISE\CONMEME\RAM0.vhd"
RAM0>
Behavioral>
ram0>
*HDLElaboration*
Elaboratingentity<
（architecture<
）fromlibrary<
work>
*HDLSynthesis*
SynthesizingUnit<
Relatedsourcefileis"
f:
/model/ise/conmeme/ram0.vhd"
Summary:
nomacro.
Unit<
synthesized.
HDLSynthesisReport
Foundnomacro
*AdvancedHDLSynthesis*
Readingcore<
ipcore_dir/RAM.ngc>
ipcore_dir/RAM1.ngc>
ipcore_dir/RAM2.ngc>
Loadingcore<
fortimingandareainformationforinstance<
your_instance_name>
your_instance_name1>
your_instance_name2>
AdvancedHDLSynthesisReport
*LowLevelSynthesis*
Optimizingunit<
...
Mappingallequations...
Buildingandoptimizingfinalnetlist...
Foundareaconstraintratioof100（+5）onblockRAM0,actualratiois0.
FinalMacroProcessing...
FinalRegisterReport
*PartitionReport*
PartitionImplementationStatus
-------------------------------
NoPartitionswerefoundinthisdesign.
*DesignSummary*
TopLevelOutputFileName:
RAM0.ngc
PrimitiveandBlackBoxUsage:
------------------------------
#BELS:
6
#GND:
3
#VCC:
#RAMS:
#RAMB8BWER:
#ClockBuffers:
#BUFGP:
#IOBuffers:
44
#IBUF:
20
#OBUF:
24
Deviceutilizationsummary:
---------------------------
SelectedDevice:
6slx45fgg484-2
SliceLogicUtilization:
SliceLogicDistribution:
NumberofLUTFlipFloppairsused:
0
NumberwithanunusedFlipFlop:
0outof0
NumberwithanunusedLUT:
NumberoffullyusedLUT-FFpairs:
Numberofuniquecontrolsets:
IOUtilization:
NumberofIOs:
45
NumberofbondedIOBs:
45outof31614%
SpecificFeatureUtilization:
NumberofBlockRAM/FIFO:
2outof1161%
NumberusingBlockRAMonly:
NumberofBUFG/BUFGCTRLs:
1outof166%
PartitionResourceSummary:
TimingReport
NOTE:
THESETIMINGNUMBERSAREONLYASYNTHESISESTIMATE.
FORACCURATETIMINGINFORMATIONPLEASEREFERTOTHETRACEREPORT
GENERATEDAFTERPLACE-and-ROUTE.
ClockInformation:
------------------
-----------------------------------+------------------------+-------+
ClockSignal|Clockbuffer（FFname）|Load|
clka|BUFGP|3|
AsynchronousControlSignalsInformation:
----------------------------------------
Noasynchronouscontrolsignalsfoundinthisdesign
TimingSummary:
---------------
SpeedGrade:
-2
Minimumperiod:
Nopathfound
Minimuminputarrivaltimebeforeclock:
2.603ns
Maximumoutputrequiredtimeafterclock:
5.693ns
Maximumcombinationalpathdelay:
TimingDetails:
Allvaluesdisplayedinnanoseconds（ns）
Timingconstraint:
DefaultOFFSETINBEFOREforClock'
clka'
Totalnumberofpaths/destinationports:
78/78
-------------------------------------------------------------------------
Offset:
2.603ns（LevelsofLogic=2）
Source:
addra<
5>
（PAD）
Destination:
your_instance_name/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SP.WIDE_PRIM9.ram（RAM）
DestinationClock:
clkarising
DataPath:
toyour_instance_name/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SP.WIDE_PRIM9.ram
GateNet
Cell:
in->
outfanoutDelayDelayLogicalName（NetName）
----------------------------------------------------
IBUF:
I->
O61.3280.875addra_5_IBUF（addra_5_IBUF）
beginscope:
'
your_instance_name:
addra<
'
RAMB8BWER:
ADDRAWRADDR100.400U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SP.WIDE_PRIM9.ram
----------------------------------------
Total2.603ns（1.728nslogic,0.875nsroute）
（66.4%logic,33.6%route）
DefaultOFFSETOUTAFTERforClock'
24/24
5.693ns（LevelsofLogic=2）
your
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