基于单片机的智能晾衣架控制系统的设计与实现外文文献原稿和译文Word格式文档下载.docx

基于单片机的智能晾衣架控制系统的设计与实现外文文献原稿和译文Word格式文档下载.docx

《基于单片机的智能晾衣架控制系统的设计与实现外文文献原稿和译文Word格式文档下载.docx》由会员分享，可在线阅读，更多相关《基于单片机的智能晾衣架控制系统的设计与实现外文文献原稿和译文Word格式文档下载.docx（17页珍藏版）》请在冰豆网上搜索。

P1.5

MOSI（usedforIn-SystemProgramming）

P1.6

MOSO（usedforIn-SystemProgramming）

P1.7

SCK（usedforIn-SystemProgramming）

Port2isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseoftheinternalpull-ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses（MOVX@DPTR）.Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses（MOVX@RI）,Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.

Port3isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseofthepull-ups.Port3receivessomecontrolsignalsforFlashprogrammingandverification.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S51,asshowninthefollowingtable.

P3.0

RXD（serialinputport）

P3.1

TXD（serialoutputport）

P3.2

INT0（externalinterrupt0）

P3.3

INT1（externalinterrupt1）

P3.4

T0（timer0externalinput）

P3.5

T1（timer1externalinput）

P3.6

WR（externaldatamemorywritestrobe）

P3.7

RD（externaldatamemoryreadstrobe）

3SpecialFunctionRegisters

Amapoftheon-chipmemoryareacalledtheSpecialFunctionRegister（SFR）spaceisshowninTable3-1.

Table3-1.AT89S51SFRMapandResetValues

0F8H

0FFH

0F0H

B

00000000

0F7H

0E8H

0EFH

0E0H

ACC00000000

0E7H

0D8H

0DFH

0D0H

PSW00000000

0D7H

0C8H

0CFH

0C0H

0C7H

0B8H

IPXX000000

0BFH

0B0H

P311111111

0B7H

0A8H

IE0X000000

0AFH

0A0H

P211111111

AUXR1XXXXXXX0

WDTRSTXXXXXXXX

0A7H

98H

SCON00000000

SBUFXXXXXXXX

9FH

90H

P111111111

97H

88H

TCON00000000

TMOD00000000

TL000000000

TL1

TH0

TH100000000

AUXRXXX00XX

8FH

80H

P011111111

SP

00000111

DP0L00000000

DP0H

DP1L00000000

DP1H00000000

PCON0XXX0000

87H

Notethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.

Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybeusedinfutureproductstoinvokenewfeatures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.

InterruptRegisters:

TheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthefiveinterruptsourcesintheIPregister.

Table3-2.AUXR:

AuxiliaryRegister

AUXRAddress=8EHResetValue=XXX00XX0b

NotBitAddressable

–

–

WDIDLE

DISRTO

DISALE

Bit

7

6

5

4

3

2

1

0

　　　Reservedforfutureexpansion

DISALEDisable/EnableALE

OperatingMode

0ALEisemittedataconstantrateof1/6theoscillatorfrequency

1ALEisactiveonlyduringaMOVXorMOVCinstruction

DISRTODisable/EnableReset-out

0ResetpinisdrivenHighafterWDTtimesout

1Resetpinisinputonly

WDIDLEDisable/EnableWDTinIDLEmode

WDIDLE

0WDTcontinuestocountinIDLEmode

1WDThaltscountinginIDLEmode

DualDataPointerRegisters:

Tofacilitateaccessingbothinternalandexternaldatamemory,twobanksof16-bitDataPointerRegistersareprovided:

DP0atSFRaddresslocations82H-83HandDP1at84H-85H.BitDPS=0inSFRAUXR1selectsDP0andDPS=1selectsDP1.TheusershouldalwaysinitializetheDPSbittotheappropriatevaluebeforeaccessingtherespectiveDataPointerRegister.

PowerOffFlag:

ThePowerOffFlag（POF）islocatedatbit4（PCON.4）inthePCONSFR.POFissetto“1”duringpowerup.Itcanbesetandrestundersoftwarecontrolandisnotaffectedbyreset.

4MemoryOrganization

MCS-51deviceshaveaseparateaddressspaceforProgramandDataMemory.Upto64KbyteseachofexternalProgramandDataMemorycanbeaddressed.

4.1ProgramMemory

IftheEApinisconnectedtoGND,allprogramfetchesaredirectedtoexternalmemory.OntheAT89S51,ifEAisconnectedtoVCC,programfetchestoaddresses0000HthroughFFFHaredirectedtointernalmemoryandfetchestoaddresses1000HthroughFFFFHaredirectedtoexternalmemory.

4.2DataMemory

TheAT89S51implements128bytesofon-chipRAM.The128bytesareaccessibleviadirectandindirectaddressingmodes.Stackoperationsareexamplesofindirectaddressing,sothe128bytesofdataRAMareavailableasstackspace.

5WatchdogTimer（One-timeEnabledwithReset-out）

TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets.TheWDTconsistsofa14-bitcounterandtheWatchdogTimerReset（WDTRST）SFR.TheWDTisdefaultedtodisablefromexitingreset.ToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister（SFRlocation0A6H）.WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.TheWDTtimeoutperiodisdependentontheexternalclockfrequency.ThereisnowaytodisabletheWDTexceptthroughreset（eitherhardwareresetorWDToverflowreset）.WhenWDToverflows,itwilldriveanoutputRESETHIGHpulseattheRSTpin.

5.1UsingtheWDT

ToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister（SFRlocation0A6H）.WhentheWDTisenabled,theuserneedstoserviceitbywriting01EHand0E1HtoWDTRSTtoavoidaWDToverflow.The14-bitcounteroverflowswhenitreaches16383（3FFFH）,andthiswillresetthedevice.WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.ThismeanstheusermustresettheWDTatleastevery16383machinecycles.ToresettheWDTtheusermustwrite01EHand0E1HtoWDTRST.WDTRSTisawrite-onlyregister.TheWDTcountercannotbereadorwritten.WhenWDToverflows,itwillgenerateanoutputRESETpulseattheRSTpin.TheRESETpulsedurationis98xTOSC,whereTOSC=1/FOSC.TomakethebestuseoftheWDT,itshouldbeservicedinthosesectionsofcodethatwillperiodicallybeexecutedwithinthetimerequiredtopreventaWDTreset.

5.2WDTDURINGPower-downandIdle

InPower-downmodetheoscillatorstops,whichmeanstheWDTalsostops.WhileinPower-downmode,theuserdoesnotneedtoservicetheWDT.TherearetwomethodsofexitingPower-downmode:

byahardwareresetorviaalevel-activatedexternalinterr