基于ad9854扫频信号源的设计翻译.docx

基于ad9854扫频信号源的设计翻译.docx

《基于ad9854扫频信号源的设计翻译.docx》由会员分享，可在线阅读，更多相关《基于ad9854扫频信号源的设计翻译.docx（12页珍藏版）》请在冰豆网上搜索。

基于ad9854扫频信号源的设计翻译

基于ad9854扫频信号源的设计-翻译

苏州大学本科生毕业设计（论文）附件:

外文文献资料与中文翻译稿

外文文献资料

收集:

苏州大学应用技术学院10电子,学号1016405013,黄海浩

IntroductiontoAD9854

GENERALDESCRIPTION

TheAD9854ispin-for-pincomTheAD9854digitalsynthesizerisahighlyintegrateddevicethatusesadvancedDDStechnology,coupledwithtwointernalhighspeed,highperformancequadratureDACstoformadigitallyprogrammableIandQsynthesizerfunction.Whenreferencedtoanaccurateclocksource,theAD9854generateshighlystable,frequency-phase,amplitude-programmablesineandcosineoutputsthatcanbeusedasanagileLOincommunications,radar,andmanyotherapplications.TheinnovativehighspeedDDScoreoftheAD9854provides48-bitfrequencyresolution（1μHztuningresolutionwith300MHzSYSCLK）.Maintaining17bitsensuresexcellentSFDR.

ThecircuitarchitectureoftheAD9854allowsthegenerationofsimultaneousquadratureoutputsignalsatfrequenciesupto150MHz,whichcanbedigitallytunedatarateofupto100millionnewfrequenciespersecond.Thesinewaveoutput（externallyfiltered）canbeconvertedtoasquarewavebytheinternal

foragileclockgeneratorapplications.Thedeviceprovidestwo14-bitcomparator

phaseregistersandasinglepinforBPSKoperation.

Forhigher-orderPSKoperation,theI/Ointerfacecanbeusedforphasechanges.The12-bitIandQDACs,coupledwiththeinnovativeDDSarchitecture,provideexcellentwidebandandnarrow-bandoutputSFDR.TheQDACcanalsobeconfiguredasauser-programmablecontrolDACifthequadraturefunctionisnotdesired.Whenconfiguredwiththecomparator,the12-bitcontrolDACfacilitatesstaticdutycyclecontrolinhighspeedclockgeneratorapplications.

Two12-bitdigitalmultiplierspermitprogrammableamplitudemodulation,on/offoutputshapedkeying,andpreciseamplitudecontrolofthequadratureoutput.Chirpfunctionalityisalsoincludedtofacilitatewidebandwidthfrequencysweepingapplications.Theprogrammable4×to20×REFCLKmultipliercircuitof

theAD9854internallygeneratesthe300MHzsystemclockfromanexternallower

第1页

苏州大学本科生毕业设计（论文）附件:

外文文献资料与中文翻译稿

frequencyreferenceclock.Thissavestheusertheexpenseanddifficultyofimplementinga300MHzsystemclocksource.

Direct300MHzclockingisalsoaccommodatedwitheithersingle-endedordifferentialinputs.Single-pinconventionalFSKandtheenhancedspectralqualitiesoframpedFSKaresupported.TheAD9854usesadvanced0.35μmCMOS

technologytoprovideahighleveloffunctionalityonasingle3.3patiblewiththeAD9852single-tonesynthesizer.Itisspecifiedtooperateovertheextendedindustrialtemperaturerangeof?

40?

Cto+85?

C.

THEORYOFOPERATION

TheAD9854quadratureoutputdigitalsynthesizerisahighlyflexibledevicethataddressesawiderangeofapplications.ThedeviceconsistsofanNCOwitha48-bitphaseaccumulator,aprogrammablereferenceclockmultiplier,inversesincfilters,

digitalmultipliers,two12-bit/300MHzDACs,ahighspeedanalogcomparator,andinterfacelogic.ThishighlyintegrateddevicecanbeconfiguredtoserveasasynthesizedLO,anagileclockgenerator,oranFSK/BPSKmodulator.

AnalogDevices,Inc.,providesatechnicaltutorialabouttheoperationaltheoryofthefunctionalblocksofthedevice.ThetutorialincludesatechnicaldescriptionofthesignalflowthroughaDDSdeviceandprovidesbasicapplicationsinformationforavarietyofdigitalsynthesisimplementations.Thedocument,ATechnicalTutorialonDigitalSignalSynthesis,isavailablefromtheDDSTechnicalLibrary,ontheAnalogDevicesDDSwebsiteat

MODESOFOPERATION

TheAD9854hasfiveprogrammableoperationalmodes.Toselectamode,threebitsinthecontrolregister（parallelAddress1Fhex）mustbeprogrammed,asdescribedinTable5.

Table5.ModeSelectionTable

Mode2Mode1Mode0Result

000Singletone

001FSK

010RampedFSK

第2页

苏州大学本科生毕业设计（论文）附件:

外文文献资料与中文翻译稿

011Chirp

100BPSK

INTERNALANDEXTERNALUPDATECLOCK

ThisupdateclockfunctioniscomprisedofabidirectionalI/Opin（Pin20）andaprogrammable32-bitdown-counter.ToprogramchangesthataretobetransferredfromtheI/ObufferregisterstotheactivecoreoftheDDS,aclocksignal（low-to-highedge）mustbeexternallysuppliedtoPin20orinternallygeneratedbythe32-bitupdateclock.

Whentheuserprovidesanexternalupdateclock,itisinternallysynchronizedwiththesystemclocktopreventapartialtransferofprogramregisterinformationduetoaviolationofdatasetuporholdtime.Thismodeallowstheusertocompletelycontrolwhenupdatedprograminformationbecomeseffective.Thedefaultmodefortheupdateclockisinternal（theinternalupdateclockcontrolregisterbitislogichigh）.Toswitchtoexternalupdateclockmode,theinternalupdateclockcontrolregiste