用状态机实现的EDA多功能数字钟课程设计VHDL代码文档格式.docx
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4)日计时器(date1)是由一个60进制的计数器构成的,具有清0、置数和计数功能。
其中reset为清0信号,当reset为0时,星期计时器清0;
set为置数信号,当set为0时,星期计时器置数,置d1的值。
clkd为驱动星期计时器工作的时钟,与enhour相连接;
date为日计时器的输出,endate为分计时器的进位信号,作为下一级的时钟输入信号,由于月份的天数存在天数不同,闰年2月的天数为28天等情况,还设计了一个润年判别器,准确显示时间。
5)月计时器(mouth)是由一个60进制的计数器构成的,具有清0、置数和计数功能。
set为置数信号,当set为0时,星期计时器置数,置mou1的值,clkmou为驱动星期计时器工作的时钟,与enday相连接;
mou为日计时器的输出,enmou为分计时器的进位信号,作为下一级的时钟输入信号。
6)计时器(year)是由一个60进制的计数器构成的,具有清0、置数和计数功能。
set为置数信号,当set为0时,星期计时器置数,置y1的值,clky为驱动星期计时器工作的时钟,与enmou相连接;
year为日计时器的输出。
VHDL程序
1、屏幕切换模块
运用状态机进行屏幕切换,分别显示年月日,以及时分秒
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncommentthefollowinglinestousethedeclarationsthatare
--providedforinstantiatingXilinxprimitivecomponents.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entitymux3is
Port(clk,Reset,sel:
instd_logic;
int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12:
INSTD_LOGIC_VECTOR(3DOWNTO0);
--rstmust
a1,a2,a3,a4,a5,a6:
outstd_logic_vector(3downto0));
endmux3;
architectureBehavioralofmux3is
TYPEstatesIS(st0,st1,st2,st3,st4,st5,st6,st7);
SIGNALSTX:
states;
begin
COM1:
PROCESS(STX,int1,int2,int3,int4,int5,int6,int7,int8,int9,int10,int11,int12)
BEGIN--决定转换状态的进程
CASESTXIS
WHENst0=>
a1<
=int1;
a2<
=int2;
a3<
=int3;
a4<
=int4;
a5<
=int5;
a6<
=int6;
WHENst1=>
=int7;
=int8;
=int9;
=int10;
=int11;
=int12;
WHENst2=>
WHENst3=>
WHENst4=>
WHENst5=>
WHENst6=>
WHENst7=>
WHENOTHERS=>
NULL;
ENDCASE;
ENDPROCESSCOM1;
REG:
PROCESS(clk,Reset,sel)--主控时序进程
BEGIN
IFReset='
1'
THENSTX<
=st0;
--异步复位
ELSIFclk='
ANDclk'
EVENTTHEN
ifsel='
then
CASESTXIS
WHENst0=>
STX<
=st1;
WHENst1=>
=st2;
WHENst2=>
=st3;
WHENst3=>
=st4;
WHENst4=>
=st5;
WHENst5=>
=st6;
WHENst6=>
=st7;
WHENst7=>
=st0;
ENDCASE;
ENDIF;
ENDif;
ENDPROCESS;
2、显示切换程序
entitymux1is
Port(clk,ina,inb,sel,Reset:
result:
outstd_logic);
endmux1;
architectureBehavioralofmux1is
TYPEstateIS(st0,st1,st2,st3,st4,st5,st6,st7);
state;
REG1:
PROCESS(ina,inb,STX)
result<
=ina;
=inb;
ENDPROCESS;
REG2:
PROCESS(clk,sel,Reset)
BEGIN
IF(Reset='
)THEN
STX<
ELSIF(clk'
EVENTANDclk='
)THEN
then
CASESTXIS
WHENst0=>
WHENst1=>
WHENst2=>
WHENst3=>
WHENst4=>
WHENst5=>
WHENst6=>
WHENst7=>
ENDCASE;
ENDIF;
endif;
ENDPROCESSREG2;
endBehavioral;
3、置数操作模块
运用状态机,进行置数操作
entitymuxis
r1,r2,r3,r4,r5,r6:
endmux;
architectureBehavioralofmuxis
r1<
r2<
='
0'
;
r3<
r4<
r5<
r6<
ifsel='
4、秒显示模块
entitysecute1is
Port(clkm,set,reset:
sec2,sec1:
inoutstd_logic_vector(3downto0);
ensec:
endsecute1;
architectureBehavioralofsecute1is
Process(clkm,reset,set)
Begin
Ifreset='
thensec2<
="
0000"
sec1<
Elsifset='
0101"
1000"
Elsif(clkm'
eventandclkm='
)then
ifsec2="
ANDsec1="
1001"
ensec<
elsifsec1="
=sec2+'
elsesec1<
=sec1+'
endif;
Endprocess;
5、分显示模块
entityminute1is
min2,min1:
enmin:
endminute1;
architectureBehavioralofminute1is
thenmin2<
min1<
ifmin2="
ANDmin1="
enmin<
elsifmin1="
=min2+'
elsemin1<
=min1+'
6、小时显示模块
entityhour1is
Port(clkh,set,reset:
hor2,hor1:
enhour:
endhour1;
architectureBehavioralofhour1is
Process(clkh,reset,set)
thenhor2<
hor1<
0010"
0011"
Elsif(clkh'
eventandclkh='
ifhor2="
ANDhor1="
enhour<
elsifhor1="
=hor2+'
elsehor1<
=hor1+'
7、日显示模块(已加入闰年判断功能)
entitydate1is
Port(clkd,set:
dat2,dat1:
endate:
enddate1;
architectureBehavioralofdate1is
Process(clkd,set)
Begin
ifset='
thendat2<
dat1<
Elsif(clkd'
eventandclkd='
)then
ifdat2="
ANDdat1="
0001"
endate<
elsifdat1="
=dat2+'
elsedat1<
=dat1+'
endate<
8、月显示模块
entitymonth1is
Port(clkn,set:
mon2,mon1:
enmon:
endmonth1;
architectureBehavioralofmonth1is
Process(clkn,set)
thenmon2<
mon1<
0110"
Elsif(clkn'
eventandclkn='
ifmon2="
ANDmon1="
enmon<
elsifmon1="
=mon2+'