计算机组成与体系结构B卷Word文档格式.docx
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闭卷;
4.本试卷共三大题,满分100分,考试时间120分钟。
题号
一
二
三
四
五
总分
得分
评卷人
I.单项选择题(2pointseach)
Answerthequestion1-2basedonthefollowinginformation:
Amemorysystemuses24-bitphysicaladdress.Ithasadirect-mappedcachewith64entries.Theblocksizeis4words(wordsizeis4bytes).Eachcacheentryhasa“validbit”,a“tagfield”,andspacefordata.
1.Thenumberofbitsreservedforthetagfieldis______.
A.14B.10C.6D.12
2.Thetotalnumberofbitsinthecacheis______.
A.26*(143)B.26*(33)C.28*(145)D.214*(33)
3.Whichoneofthefollowingaboutone-addressinstructionistrue?
_____
A.One-addressinstructionhasonlyoneoperand
B.One-addressinstructionmayhaveoneoperandortwooperands
C.One-addressinstructionhastwooperands,andtheotheroperandisprovidedimplicitly
D.One-addressinstructionmayhavethreeoperands,andtheothertwooperandsareprovidedimplicitly
4.CPUresponsestheinterruptrequest______.
A.afteritcompletesitsfetchcycle
B.afteritcompletesitsexecutioncycle
C.whentheinterruptsourceissuestheinterruptrequest
D.whenthebusisnotbusy
5.Theadvantageofcarry-lookaheadadderis______.
A.Optimizethestructureoftheadder
B.Savehardwareparts
C.Acceleratethegenerationofthecarries
D.Augmentthestructureoftheadder
6.Inmicroprogram-controlledmachines,therelationshipbetweenthemachineinstructionandthemicroinstructionis______.
A.amachineinstructionisexecutedbyamicroinstruction
B.amicroinstrucitoniscomposedofseveralmachineinstructions
C.amachineinstructionisinterpretedbyamicroroutinecomposedofmicroinstructions
D.amicroroutineisexecutedbyamachineinstruction
7.OncetheDMAcontrollerobtainsaccesstothesystembus,ittransfersonebyteofdataandthenreturnsthecontrolofsystemtotheprocessor.ThisDMAtransfermodeis_____.
A.BurstModeC.CycleStealingMode
B.BlockModeD.TransparentMode
8.AssumethatthecapacityofakindofSRAMchipis16K×
32,sothesumofaddresslinesanddatalinesofthischipis______.
A.48B.46C.36D.32
9.Assumethatthemultiplicandis110011andthemultiplieris101110.IfmultiplythemusingtheBoothalgorithm,thentheBoothrecodingmultiplieris______.
A.–1–100–10C.–1+100–10
B.+1–100+10D.1+100–10
10.Themicroroutinesforallinstructionsintheinstructionsetofacomputerarestoredinthe.
A.memorycontrollerC.controlstore
B.mainmemoryD.cache
11.______istheprocessbywhichthenextdevicetobecomethebusmasterisselectedandbusmastershipistransferredtoit.
A.BusprotocolC.Bustiming
B.BusarbitrationD.Bustransceiver
12._____has/haveexternalfragmentationproblem.
A.PagingC.Segmentationwithpaging
B.SegmentationD.Segmentationandsegmentationwithpaging
13.Therangeandaccuracyoffloating-pointnumbersdependon______respectively.
A.Thesizeofexponentandtherepresentationofmantissa
B.Thesizeofexponentandthesizeofmantissa
C.Thesizeofmantissaandtherepresentationofexponent
D.Thesizeofmantissaandthesizeofexponent
14.Inasynchronousbus,controllingofdatatransferonthebusisbasedon______.
A.acommonclocksignalonly
B.ahandshakesignalonly
C.bothclocksignalandhandshakesignal
D.eitherclocksignalorhandshakesignal
15.Whichoneofthefollowingisnotusedtopreventdatahazards?
_______
A.Bypassing
B.Forwarding
C.Stall
D.FreezeorFlush
II.简答题(5pointseach)
1.WhatisthedifferencebetweenDRAMandSRAM,intermsofcharacteristicssuchasspeed,size,costandapplication?
Solution:
2.Inwhatcircumstancewillarithmeticoverflowoccurwhentwointegersrepresentedby2'
scomplementformareadded?
Andwriteoutthelogicexpressiontodetectoverflow.
3.Describetheprocessofinterruptprocessing.
4.(5points)Whataretheadvantagesanddisadvantagesofhardwiredandmicroprogrammedcontrol?
III.综合题(10pointseach)
1.Usingnonrestoringdivisionalgorithm,performtheoperationsA÷
Bonthe5-bitunsignednumbersA=10101andB=00101.Writethecomputationprocessesinacomputermachine.
2.
Abyte-addressablecomputerhas16addresslines,8datalines,WRsignal(read/writecontrolsignal)andMREQsignal(accessmemorycontrolsignal).Itsaddressspaceincludes:
a)systemprogramarearangingfrom0to8191(decimal)
b)userprogramarearangingfrom8192to32767(decimal)
c)andthelast2Kaddressspaceforsystemprogramworkingarea
Therearesomememorychips:
ROM:
8K×
8
SRAM:
16K×
1,2K×
8,4K×
8,8K×
(1)Pleasespecifyhowmanychipstoselecttodesignthemainmemoryofthecomputer.
(2)Drawthelogicstructurefigureofthemainmemory,andtheconnectionbetweenthemainmemoryandCPU.
3.Thefollowingfiguregivespartofthemicroinstructionsequencecorrespondingtooneofthemachineinstructionsofamicroprogrammedcomputer.MicroinstructionBisfollowedbyC,E,F,orI,dependingonbitsb6andb5ofthemachineinstructionregister.Comparethetwopossibleimplementationsdescribedbelow.
(1)Microinstructionsequencingisaccomplishedbymeansofamicroprogramcounter.Branchingisachievedbymicroinstructionsoftheform:
Ifb6b5branchtoX
whereb6b5isthebranchconditionandXisthebranchaddress.
(2)Sameas
(1)exceptthatthebranchmicroinstructionhastheform:
BranchtoX,OR
WhereXisabasebranchaddress.Thebranchaddressismodifiedby
bit-ORingofbitsb5andb6withtheappropriatebitswithX.
A
B
b6b5=11
b6b5=10
b6b5=00
b6b5=01
C
E
F
I
D
G
H
J
4.Consideracomputerwith4M×
16memorycontains97instructionsinitsinstructionset.Theopcodelengthisfixed,andtheaddressingmodesaredirect,indirect,immediate,index,andrelative.(Assumethattheinstructionlengthequalstowordlength)
(1)Drawthefigureofone-addressinstructionformat,andspecifythefunctionofeachfield.
(2)Specifythemaxrangeofthedirectaddressingmode.(indecimal)
(3)Specifytheaddressingrangeofone-levelindirectaddressingmode.(indecimal)
(4)Specifytheoffsetoftherelativeaddressingmode.(indecimal)
5.Alogiccircuitisneededtoimplementtheprioritynetworkshownlikethefollowingfigure.Thenetworkhandlesthreeinterruptrequestlines.WhenarequestisreceivedonlineINTRi,thenetworkgeneratesanacknowledgementonlineINTAi.Ifmorethanonerequestisreceived,onlythehighest-priorityrequestisacknowledged,wheretheorderingofpriorityis:
priorityofINTR1>
priorityofINTR2>
priorityofINTR3.
(1)GiveatruthtableforeachoftheoutputsINTA1,INTA2,andINTA3.
(2)GivelogicexpressionsofINTA1,INTA2,INTA3andalogiccircuitforimplementingthisprioritynetwork.