EDA电子钟课程设计Word文档格式.docx
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instd_logic;
dout:
outstd_logic_vector(7downto0);
c:
outstd_logic);
endcnt_h;
architecturertlofcnt_his
signalt:
std_logic_vector(7downto0);
begin
process(en,clk,clr)
variablet:
begin
ifen='
1'
then--异步使能
ifclk'
eventandclk='
then
t:
=t+1;
ift(3downto0)=X"
A"
then--个位等于10则十位加1
t(7downto4):
=t(7downto4)+1;
t(3downto0):
=X"
0"
;
--个位清零
endif;
ift>
X"
23"
then--大于23清零
00"
ifclr='
then--异步清零
dout<
=t;
endprocess;
endrtl;
时计数器模块仿真波形如下
从仿真波形可知,当计数到23时,下一个时钟上升沿到来时就清零了,符合设计要求。
时计数模块框图如下
2.分及秒计数模块
分及秒计数模块也是一个2位10进制计数器,记数到59清零。
entitycnt_sis
bufferstd_logic_vector(7downto0);
endcnt_s;
architecturertlofcnt_sis
elsifclk'
then
ifdout(3downto0)<
9then
dout(3downto0)<
=dout(3downto0)+1;
c<
='
0'
elsifdout(7downto4)<
5then
dout(7downto4)<
=dout(7downto4)+1;
else
elsedout<
="
ZZZZZZZZ"
分和秒计数器模块仿真波形如下
从仿真波形可知,当计数到59时,下一个时钟上升沿到来时就清零了,并且产生进位信号,符合设计要求。
分和秒计数模块框图如下
3.按键消抖动模块
按键消抖动有很多方案,这里选择的是计数消抖,即只当有效电平到来后开始计数,当计数值大于一定值后再输出该有效电平,否则不输出,从而达到消抖目的。
entityhaoinis
port(din,clk:
endhaoin;
architecturertlofhaoinis
process(din)
integerrange0to63:
=0;
ifdin='
then
10then
t:
=t-1;
entityringis
port(
clk:
instd_logic;
clk500:
clk1k:
beep:
endring;
architecturertlofringis
process(clk)
std_logic;
variablen:
integerrange0to15:
=nott;
n:
=n+1;
ift='
andn<
11then
beep<
=clk500;
elsifn=11then
=clk1k;
elsebeep<
Z'
libraryIEEE;
useIEEE.std_logic_1164.all;
useIEEE.std_logic_arith.all;
useIEEE.std_logic_unsigned.all;
entityclockis
SA:
SB:
SC:
SD:
clk1:
bufferstd_logic_vector(23downto0);
--seg_data:
--seg_com:
outstd_logic_vector(3downto0);
outstd_logic
--led:
outstd_logic_vector(3downto0)
);
endentityclock;
architecturertlofclockis
componentcnt_sis
endcomponent;
componentcnt_his
bufferstd_logic_vector(7downto0)
--componentsegmainis
--port(clk,reset_n:
--datain:
instd_logic_vector(15downto0);
--seg_data:
--seg_com:
outstd_logic_vector(3downto0));
--endcomponent;
--componentringis
--port(en:
--clk:
--clk500:
--clk1k:
--beep:
componenthaoinis
componentnaolingis
port(h,m:
instd_logic_vector(7downto0);
clk4hzh,clk4hzm:
sys_en,sys_rst:
h_o,m_o:
outstd_logic_vector(7downto0);
signalreg_h:
signalreg_m:
signalreg_s:
signalreg_m_s:
std_logic_vector(7downto0):
59"
signalreg_m_m:
signalreg_m_h:
signalclk_h:
std_logic;
signalclk_m:
signalclk_s:
signalc_s:
signalc_m:
signalc_h:
signalsys_clk1:
signalsys_clk4:
signalsys_clk64:
signalsys_clk500:
signalsys_clk1k:
signalclki:
integer:
=750000;
signalsys_rst:
std_logic:
signalsys_en:
signalclk_ring,mh:
signalSAc,SBc,SCc,SDc:
signalen_r:
signalNL_reg_h,NL_reg_m:
signalNL_ring:
signalsys_clk4_NL_h,sys_clk4_NL_m:
h:
cnt_hportmap(en=>
sys_en,clk=>
clk_h,clr=>
sys_rst,dout=>
reg_h);
m:
cnt_sportmap(en=>
clk_m,clr=>
reg_m,c=>
c_m);
s:
sys_clk1,clr=>
SCc,dout=>
reg_s,c=>
c_s);
--sled:
segmainportmap(clk=>
clk1,reset_n=>
SCc,seg_data=>
seg_data,seg_com=>
seg_com,datain=>
dout(15downto0));
--ring0:
ringportmap(en=>
en_r,clk=>
clk_ring,clk500=>
sys_clk500,clk1k=>
sys_clk1k,beep=>
beep);
haoin1:
haoinportmap(SA,sys_clk64,SAc);
haoin2:
haoinportmap(SB,sys_clk64,SBc);
haoin3:
haoinportmap(SC,sys_clk64,SCc);
haoin4:
haoinportmap(SD,sys_clk64,SDc);
NL:
naolingportmap(beep=>
NL_ring,h=>
reg_h,m=>
reg_m,clk4hzh=>
sys_clk4_NL_h,clk4hzm=>
sys_clk4_NL_m,sys_en=>
sys_en,sys_rst=>
sys_rst,h_o=>
NL_reg_h,m_o=>
NL_reg_m);
=clk_ringandmh;
--led<
=reg_s(3downto0);
p_sys_clk:
process(clk1)
variablet1,t4,t64,t500,t1k:
integerrange0to50000000;
ifclk1'
eventandclk1='
t1:
=t1+1;
t4:
=t4+1;
t64:
=t64+1;
t500:
=t500+1;
t1k:
=t1k+1;
ift1=clki/2then
sys_clk1<
=notsys_clk1;
ift4=clki/8then
sys_clk4<
=notsys_clk4;
ift64=clki/128then
sys_clk64<
=notsys_clk64;
ift500=clki/1000then
sys_clk500<
=notsys_clk500;
ift1k=clki/2000then
sys_clk1k<
=notsys_clk1k;
endprocessp_sys_clk;
p_c:
process(SAc,SBc,SCc,SDc)
ifSAc='
andSDc='
clk_h<
=sys_clk4;
=c_m;
sys_clk4_NL_h<
ifSBc='
clk_m<
=c_s;
sys_clk4_NL_m<
ifSDc='
dout(7downto0)<
=reg_s;
dout(15downto8)<
=reg_m;
dout(23downto16)<
=reg_h;
=NL_reg_m;
=NL_reg_h;
endprocessp_c;
P_ring:
process(reg_m,reg_s,sys_clk1k)
variableclk_ring_t:
variablet:
std_logic_vector(3downto0);
ifreg_m=X"
and(reg_s=X"
50"
orreg_s=X"
52"
54"
56"
58"
)then
clk_ring_t:
=sys_clk500;
elsifreg_m=X"
andreg_s=X"
=sys_clk1k;
elseclk_ring_t:
ifNL_ring='
ifsys_clk1k'
eventandsys_clk1k='
1thenmh<
clk_ring<
=clk_ring_t;
endprocessp_ring;