外文翻译基于单片机的频率计设计.docx

外文翻译基于单片机的频率计设计.docx

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外文翻译基于单片机的频率计设计

原文：

ThisdesigntakeatMCS-51monolithicintegratedcircuitasthecorefullusehardwaresourcedesign'sonekindoffrequencymeter,thisfrequencymeterwillbemeasuredfirstthatsignalenlargementreshapingprocessing,turnssatisfiesTTL/whichthemonolithicintegratedcircuitI/OmouthacceptstheCMOScompatiblesignalfrommonolithicintegratedcircuit'sT1inputportinputdirectsummationpulsenumber,themonolithicintegratedcircuitinteriortimerfixedtimeis1S,bynowaccumulatedthepulsenumbernamelyforismeasuredthesignalthefrequency.Finallypassesthroughmonolithicintegratedcircuitprocessingtodelivertothelcdliquidcrystaldisplaymonitordemonstration.

CentralProcessingUnitDesigns

TheCPUisthekeycomponentofadigitalcomputer.Itspurposeistodecodeinstructionreceivedfrommemoryandperformtransfers,arithmetic,logic,andcontroloperationswithdatastoredininternalregisters,memory,orI/Ointerfaceunits.Externally,theCPUprovidesoneormorebusesfortransferringinstructions,data,andcontrolinformationtoandfromcomponentsconnectedtoit.Inthegenericcomputeratthebeginningofchapter1,theCPUisapartoftheprocessorandisheavilyshaded.CPUs,however,mayalsoappearincomputers.Small,relativelysimplecomputerscalledmicrocontrollersareusedincomputersandinotherdigitalsystemstoperformlimitedorspecializedtasks.Forexample,amicrocontrollerispresentinthekeyboardandinthemonitorinthegenericcomputer;thus,thesecomponentsarealsoshaded.Insuchmicrocontrollers,theCPUmaybequitedifferentfromthosediscussedinthischapter.Thewordlengthsmaybeshort（say,fouroreightbits）,thenumberofregisterssmall,andtheinstructionsetslimited.Performance,relativelyspeaking,ispoor,butadequateforthetask.Mostimportant,thecostofthesemicrocontrollersisverylow,makingtheirusecosteffective.

Inthefollowingpages,weconsidertwocomputerCPUs,oneforacomplexinstructionsetcomputer（CISC）andtheotherforareducedinstructionsetcomputer（RISC）.Afteradetailedexaminationofthedesigns,wecomparetheperformanceofthetwoCPUsandpresentabriefoverviewofsomemethodsusedtoenhancethatperformance.Finally,werelatethedesignideasdiscussedtogeneraldigitalsystemdesign.

1、Thecomplexinstructionsetcomputer

Thefirstdesignwepresentisforacomplexinstructionsetcomputerwithanon-pipelineddatapathandmicroprogrammedcontrolunit.Webeginbydescribingtheinstructionsetarchitecture,includingtheCPUregisterset,instructionformats,andaddressingmodes.TheCISCnatureoftheinstructionsetarchitectureisdemonstratedbyitsmemory-to-memoryaccessfordatamanipulationinstructions,eightaddressingmodes,twoinstructionformatlengths,andinstructionsthatrequiresignificantsequencesofoperationsfortheirexecution.

WedesignadatapathforimplementingtheCISCarchitecture.ThedatapathisbasedontheoneinitiallydescribedinSection7-9andincorporatedintoaCPUinsection8-10.modificationsaremadetotheregisterfile,thefunctionunit,andthebusestosupportthepresentinstructionsetarchitecture.

Oncethedatapathhasbeenspecified,acontrolunitisdesignedtocompletetheimplementationoftheinstructionsetarchitecture.Thedesignofthecontrolunitmustinvolveacoordinateddefinitionofboththehardwareorganizationandthemicroprogramorganization.Inparticular,dividingthemicroprogramintomicroroutines,whileatthesametimedesigningthesequencerwithwhichtheyinteract,isakeypartofthedesign.Eventheinstructionfieldsandopposedaretiedtothiscoordinatedeffort.Followingthedefinitionofthehardwareandmicrocodeorganizations,wedetailessentialpartsofthemicrocodeandthemicroroutinesforrepresentativeoperations.

Instructionsetarchitecture

Figure10-1showstheCISCregistersetaccessibletotheprogrammer.Allregistershave16bits.Theregisterfilehaseightregisters,R0thoughR7.R0isaspecialregisterthatalwayssuppliesthevaluezerowhenitisusedasasourceanddiscardstheresultwhenitisusedasadestination.

Inadditionaltotheregisterfile,thereisaprogramcounterPCandstackpointerSP.Thepresenceofastackpointerindicatesthatamemorystackisapartofthearchitecture.thefinalregisteristheprocessorstatusregisterPSR,whichcontainsinformationonlyinitsrightmostthefivebits;theremainderoftheregisterisassumedtocontainzero.ThePSRcontainsthefourstoredstatusbitvaluesZ,N,C,andVinpositions3through0,respectively.Inadditional,astoredinterruptenablebitEIappearsinposition4.

Table10-1containsthe42operationsperformedbytheinstructions.Eachoperationhasamnemonicandacarefullyselectedoppose.Theoperationsaredividedinto