简单计算机系统课程设计计算机组成实验C.docx
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简单计算机系统课程设计计算机组成实验C
简单计算机系统课程设计计算机组成实验C
《计算机组成实验C》
课程设计
适用专业:
电子信息类专业
专业:
****
班级:
********
学号:
********
姓名:
***
指导教师:
***
实验学期:
-第1学期
西南交通大学
信息科学与技术学院
简化计算机系统的设计
一.实验目的:
经过学习简单的指令系统及其各指令的操作流程,用VHDL语言实现简单的处理器模块,并经过调用存储器模块,将处理器模块和存储器模块连接形成简化的计算机系统。
二.实验内容
1.用VHDL语言实现简单的处理器模块。
2.调用存储器模块设计256×16的存储器模块。
3.将简单的处理器模块和存储器模块连接形成简单的计算机系统。
4.将指令序列存入存储器,然后分析指令执行流程。
三.预习要求:
1、学习简单指令集。
2、学习各指令的操作流程。
四.实验报告
1.BLOCK图
图1原理图
内存文件:
图2内存文件.Mif
2.程序设计
LIBRARYieee;
USEieee.std_logic_1164.ALL;
PACKAGEmypackIS
CONSTANTidle:
std_logic_vector(3DOWNTO0):
="0000";
CONSTANTload:
std_logic_vector(3DOWNTO0):
="0001";
CONSTANTmove:
std_logic_vector(3DOWNTO0):
="0010";
CONSTANTaddx:
std_logic_vector(3DOWNTO0):
="0011";
CONSTANTsubp:
std_logic_vector(3DOWNTO0):
="0100";
CONSTANTandp:
std_logic_vector(3DOWNTO0):
="0101";
CONSTANTorp:
std_logic_vector(3DOWNTO0):
="0110";
CONSTANTxorp:
std_logic_vector(3DOWNTO0):
="0111";
CONSTANTshrp:
std_logic_vector(3DOWNTO0):
="1000";
CONSTANTshlp:
std_logic_vector(3DOWNTO0):
="1001";
CONSTANTswap:
std_logic_vector(3DOWNTO0):
="1010";
CONSTANTjmp:
std_logic_vector(3DOWNTO0):
="1011";
CONSTANTjz:
std_logic_vector(3DOWNTO0):
="1100";
CONSTANTread:
std_logic_vector(3DOWNTO0):
="1101";
CONSTANTwrite:
std_logic_vector(3DOWNTO0):
="1110";
CONSTANTstop:
std_logic_vector(3DOWNTO0):
="1111";
ENDmypack;
LIBRARYieee;
USEieee.std_logic_1164.ALL;
USEieee.std_logic_unsigned.ALL;
USEWORK.mypack.ALL;
------------------------cpu实体声明---------------------------------
ENTITYcpu2IS
PORT(
reset:
INstd_logic;--清零信号低有效
clock:
INstd_logic;--时钟信号
Write_Read:
OUTstd_logic;--读写信号,'1'为写
M_address:
OUTstd_logic_vector(11DOWNTO0);--地址线
M_data_in:
INstd_logic_vector(7DOWNTO0);--数据输入线
M_data_out:
OUTstd_logic_vector(7DOWNTO0);--数据输出线
overflow:
OUTstd_logic);--溢出标志
ENDcpu2;
------------------------cpuRTL级行为描述--------------------------------
ARCHITECTURERTLofcpu2IS
SIGNALIR:
std_logic_vector(15DOWNTO0);--指令寄存器
SIGNALMDR:
std_logic_vector(7DOWNTO0);--数据寄存器
SIGNALMAR:
std_logic_vector(11DOWNTO0);--地址寄存器
SIGNALstatus:
integerRANGE0TO6;--状态寄存器
BEGIN
status_change:
PROCESS(reset,clock,status)
BEGIN
IFreset='0'THENstatus<=0;
ELSIFclock'EVENTANDclock='0'THEN
CASEstatusIS
WHEN0=>
status<=1;
WHEN1=>
IFIR(15DOWNTO12)=StopTHEN
status<=1;
ELSE
status<=2;
ENDIF;
WHEN2=>
CASEIR(15DOWNTO12)IS
WHENRead|Write|Jmp|Jz|Swap=>
status<=3;
WHENOTHERS=>
status<=0;
ENDCASE;
WHEN3=>
IFIR(15DOWNTO12)=SwapTHEN
status<=0;
ELSE
status<=4;
ENDIF;
WHEN4=>
status<=5;
WHEN5=>
CASEIR(15DOWNTO12)IS
WHENRead|Write=>
status<=6;
WHENOTHERS=>
status<=0;
ENDCASE;
WHENOTHERS=>
status<=0;
ENDCASE;
ELSE
NULL;
ENDIF;
ENDPROCESSstatus_change;
seq:
PROCESS(reset,clock)
VARIABLEPC:
std_logic_vector(11DOWNTO0);--程序计数器
VARIABLER0,R1,R2,R3:
std_logic_vector(7DOWNTO0);--通用寄存器
VARIABLEA:
std_logic_vector(7DOWNTO0);--临时寄存器
VARIABLEtemp:
std_logic_vector(8DOWNTO0);--临时变量
BEGIN
IF(reset='0')THEN--清零
IR<=(OTHERS=>'0');
PC:
=(OTHERS=>'0');
R0:
=(OTHERS=>'0');
R1:
=(OTHERS=>'0');
R2:
=(OTHERS=>'0');
R3:
=(OTHERS=>'0');
A:
=(OTHERS=>'0');
MAR<=(OTHERS=>'0');
MDR<=(OTHERS=>'0');
ELSIF(clock'eventANDclock='1')THEN
overflow<='0';
CASEstatusIS
WHEN0=>--状态0
IR<=M_data_in&"00000000";--取指令
PC:
=PC+1;--程序计数器加1
WHEN1=>--状态1
IF(IR(15DOWNTO12)/=stop)THEN
MAR<=PC;
ENDIF;
CASEIR(15DOWNTO12)IS
WHENload=>
R0:
="0000"&IR(11DOWNTO8);
WHENshlp|shrp=>
CASEIR(11DOWNTO10)IS--RxtoA
WHEN"00"=>A:
=R0;
WHEN"01"=>A:
=R1;
WHEN"10"=>A:
=R2;
WHENOTHERS=>A:
=R3;
ENDCASE;
WHENMove|addx|subp|andp|orp|xorp|Swap=>
CASEIR(9DOWNTO8)IS--RytoA
WHEN"00"=>A:
=R0;
WHEN"01"=>A:
=R1;
WHEN"10"=>A:
=R2;
WHENOTHERS=>A:
=R3;
ENDCASE;
WHENOTHERS=>NULL;
ENDCASE;
WHEN2=>--状态2CASEIR(15DOWNTO12)IS
WHENaddx=>--Rx:
=Rx+A;
CASEIR(11DOWNTO10)IS
WHEN"00"=>
temp:
=(R0(7)&R0(7DOWNTO0))+(A(7)&A(7DOWNTO0));
R0:
=temp(7DOWNTO0);
overflow<=temp(8)XORtemp(7);
WHEN"01"=>
temp:
=(R1(7)&R1(7DOWNTO0))+(A(7)&A(7DOWNTO0));
R1:
=temp(7DOWNTO0);
overflow<=temp(8)XORtemp(7);
WHEN"10"=>
temp:
=(R2(7)&R2(7DOWNTO0))+(A(7)&A(7DOWNTO0));
R2:
=temp(7DOWNTO0);
overflow<=temp(8)XORtemp(7);
WHENOTHERS=>
temp:
=(R3(7)&R3(7DOWNTO0))+(A(7)&A(7DOWNTO0));
R3:
=temp(7DOWNTO0);
overflow<=temp(8)XORtemp(7);
ENDCASE;
WHENsubp=>--Rx:
=Rx-A;
CASEIR(11DOWNTO10)IS
WHEN"00"=>
temp:
=(R0(7)&R0(7DOWNTO0))+NOT(A(7)&A(7DOWNTO0))+1;
R0:
=temp(7DOWNTO0);
overflow<=temp(8)XORtemp(7);
WHEN"01"=>
temp:
=(R1(7)&R1(7DOWNTO0))+NOT(A(7)&A(7DOWNTO0))+1;
R1:
=temp(7DOWNTO0);
overflow<=temp(8)XORtemp(7);
WHEN"10"=>
temp:
=(R2(7)&R2(7DOWNTO0))+NOT(A(7)&A(7DOWNTO0))+1;
R2:
=temp(7DOWNTO0);
overflow<=temp(8)xortemp(7);
WHENOTHERS=>
temp:
=(R3(7)&R3(7DOWNTO0))+NOT(A(7)&A(7DOWNTO0))+1;
R3:
=temp(7DOWNTO0);
overflow<=temp(8)XORtemp(7);
ENDCASE;
WHENmove=>
CASEIR(11DOWNTO10)IS
WHEN"00"=>R0:
=A;
WHEN"01"=>R1:
=A;
WHEN"10"=>R2:
=A;
WHENOTHERS=>R3:
=A;
ENDCASE;
WHENshrp=>
CASEIR(11DOWNTO10)IS
WHEN"00"=>R0:
='0'&A(7DOWNTO1);
WHEN"01"=>R1:
='0'&A(7DOWNTO1);
WHEN"10"=>R2:
='0'&A(7DOWNTO1);
WHENOTHERS=>R3:
='0'&A(7DOWNTO1);
ENDCASE;
WHENshlp=>
CASEIR(11DOWNTO10)IS
WHEN"00"=>R0:
=A(6DOWNTO0)&'0';
WHEN"01"=>R1:
=A(6DOWNTO0)&'0';
WHEN"10"=>R2:
=A(6DOWNTO0)&'0';
WHENOTHERS=>R3:
=A(6DOWNTO0)&'0';
ENDCASE;
WHENandp=>--Rx:
=RxANDA;
CASEIR(11DOWNTO10)IS
WHEN"00"=>R0:
=R0ANDA;
WHEN"01"=>R1:
=R1ANDA;
WHEN"10"=>R2:
=R2ANDA;
WHENOTHERS=>R3:
=R3ANDA;
ENDCASE;
WHENorp=>--Rx:
=RxORA;
CASEIR(11DOWNTO10)IS
WHEN"00"=>R0:
=R0ORA;
WHEN"01"=>R1:
=R1ORA;
WHEN"10"=>R2:
=R2ORA;
WHENOTHERS=>R3:
=R3ORA;
ENDCASE;
WHENxorp=>--Rx:
=RxXORA;
CASEIR(11DOWNTO10)IS
WHEN"00"=>R0:
=R0XORA;
WHEN"01"=>R1:
=R1XORA;
WHEN"10"=>R2:
=R2XORA;
WHENOTHERS=>R3:
=R3XORA;
ENDCASE;
WHENSwap=>--Swap:
RxtoRy;
CASEIR(11DOWNTO8)IS
WHEN"0100"=>R0:
=R1;
WHEN"1000"=>R0:
=R2;
WHEN"1100"=>R0:
=R3;
WHEN"0001"=>R1:
=R0;
WHEN"1001"=>R1:
=R2;
WHEN"1101"=>R1:
=R3;
WHEN"0010"=>R2:
=R0;
WHEN"0110"=>R2:
=R1;
WHEN"1110"=>R2:
=R3;
WHEN"0111"=>R3:
=R1;
WHEN"1011"=>R3:
=R2;
WHEN"0011"=>R3:
=R0;
WHENOTHERS=>NULL;
ENDCASE;
WHENOTHERS=>NULL;
ENDCASE;
WHEN3=>--状态3
CASEIR(15DOWNTO12)IS
WHENSwap=>--Swap:
AtoRx
CASEIR(11DOWNTO10)IS
WHEN"00"=>R0:
=A;
WHEN"01"=>R1:
=A;
WHEN"10"=>R2:
=A;
WHENOTHERS=>R3:
=A;
ENDCASE;
WHENjmp|Jz|Read|Write=>
IR(7DOWNTO0)<=M_data_in;--取双字节指令的后半部分
PC:
=PC+1;
WHENOTHERS=>NULL;
ENDCASE;
WHEN4=>--状态4
CASEIR(15DOWNTO12)IS
WHENjmp=>--无条件转移指令
PC:
=IR(11DOWNTO0);
MAR<=IR(11DOWNTO0);
WHENJz=>--条件转移指令
IF(R0="00000000")then
PC:
=IR(11DOWNTO0);
MAR<=IR(11DOWNTO0);
else
MAR<=PC;
ENDIF;
WHENRead=>
MAR<=IR(11DOWNTO0);
WHENWrite=>
MAR<=IR(11DOWNTO0);
MDR<=R0;
WHENOTHERS=>NULL;
ENDCASE;
WHEN5=>--状态5
MAR<=PC;
WHEN6=>--状态6
CASEIR(15DOWNTO12)IS
WHENRead=>R0:
=M_data_in;
WHENOTHERS=>NULL;
ENDCASE;
ENDCASE;
ENDIF;
ENDprocessseq;
comb:
PROCESS(reset,status)
BEGIN
IF(reset='1'ANDstatus=5ANDIR(15DOWNTO12)=Write)THENWrite_Read<='1';
ELSE
Write_Read<='0';
ENDIF;
ENDPROCESScomb;
M_address<=MAR;
M_data_out<=MDR;
ENDRTL;
3.仿真波形图
图3波形图1
图4波形图2
解释如下:
图5指令含义
4.实验感想
经过本实验我学到很多有用知识,不但提高了我的系统设计和软件编程的能力,还让我对计算机组成原理实验课程有了更一步的掌握和认识。
在本课程设计中,除了对CPU内部运算器,控制器以及存储器之间的联系与分工合作的了解之外,在建立波形图时,由于受平日建图的影响,忘记添加CPU内部寄存器组,另外在添加寄存器信号后,还要将相同的划成一个GROUP,在这之前的练习中,我是没有接触过的。
这次练习掌握的一些新知识,相信在未来对我会有巨大帮助。