VHDL数字锁实验报告英文版.docx
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VHDL数字锁实验报告英文版
《VHDL与数字系统设计》课程设计报告
名称：
VHDL与数字系统设计
题目：
数字锁
院系：
班级：
学号：
学生姓名：
指导教师：
成绩：
日期：
年月日
一、实验目的
1.Todesignafinitestatemachineforadigitallock.
2.TolearntouseHDLortheStateEditortodefineafinitestatemachine.
3.ToimplementthefinitestatemachineofthedigitallockonaFPGAorCPLD
4.LearnpracticalissuesrelatedtotimingandtestingofasynchronousFSM:
generatingasinglesynchronousinputpulsewhenpressingapush-buttonsynchronizationofinputs.
5.Toexperimentallychecktheoperationofthelock.
二、实验类型
SynthesisandDesign
三、实验仪器
ComputerwiththesoftwareQuartusII5.0,Experimentalbox
四、实验原理
Itisacomplexdesign.YouneedtouseallyourknowledgeaboutVHDLtocompletethedesign.
（一）Youneedtodesignadigitallockthathasthreeinputpush-buttons:
A,BandC.Assumethatthebuttonscannotbepressedsimultaneously（anelectromechanicalinterlockguaranteesthis）.Thelockshouldhavethefollowingfeatures:
1.WhenthecombinationB-C-A-Chasbeenpressed,asignalUNLOCKisassertedthatcausesthelocktoopen.
2.Oncethelockisopen,onecanclosethelockbypressinganykey.
3.ToresetthelocktoitsinitialstateonecanpressthesequenceA-Afromanystate,exceptthealarmstateortheresetstate.
4.Inordertopreventtamperingwiththelock,anALARMwillgooff afterpressingawrongbutton.However,inordertomakeithardertofigureouttherightsequence,wedon'twantthealarmtogooffafterthefirstwrongbuttonhasbeenpressed.Instead,thealarmshouldgooffafterpressing4buttons,aslongasoneofthe4buttonspressedisawrongone（e.g.thesequencesB-C-B-A,A-B-C-A,C-C-B-A,A-A-B-C,etc.wouldtriggerthealarm）.
5.TheonlywaytogetoutofthealarmstateisbypressingtheC-Asequence.
Useasfewstatesaspossiblewithoutcompromisingtheoperationorsecurityofthelock.Theprojectinvolvesaconsiderabledesigncomponentaswellasimplementationissues.Inordertogiveyourselfenoughtimetodebugandimplementthedigitallock,youshouldstartearlyanddomostofthedesignworkduringthepre-lab.
（二）
thestatemachineis:
present_state
condition
next_state
Out_put
S0（LOCKRESET）
R
S0
U:
0
A:
0
X:
0000
B
S1
A或C
S3
S1（B）
R
S0
U:
0
A:
0
X:
0001
C
S6
A
S4
B
S5
S2（alarm+C）
RORB
S11
U:
0A:
1
X:
0010
A
S4
C
S2
S3（C,A）
R
S0
U:
0
A:
0
X:
0011
A
S4
BORC
S9
S4（AA,BA,CA）
A
S0
U:
0A:
0
X:
0100
BORC
S8
S5（AC,AB,BB
CB,CC）
AORR
S0
U:
0A:
0
X:
0101
BORC
S9
S6（BC）
R
S0
U:
0A:
0
X:
0110
A
S8
BORC
S9
S7（ABA,ACA,BBA,
CBA,CCA）
AORR
S0
U:
0A:
0
X:
0111
BORC
S11
S8（BCA）
AORR
S0
U:
0A:
0
X:
1000
C
S10
B
S11
S9（其他三位数）
R
S0
U:
0A:
0X:
1001
AORBORC
S11
S10（unlockBCAC）
RORAORCORB
S0
U:
1A：
0X：
1010
S11（ALARM）
C
S2
A：
1U：
0
X:
1011
RORAORB
S11
五、实验内容
ThedesignusingVHDLlanguage:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitydigital_lockis
port（a,b,c,r:
instd_logic;
clk:
instd_logic;
alarm,unlock,f:
outstd_logic;
led:
outstd_logic_vector（6downto0））;
endentitydigital_lock;
architectureaofdigital_lockis
componentfanis
port（a,b,c,d:
INstd_logic;
aa,bb,cc,dd:
outstd_logic）;
endcomponent;
componentqudouis
port（clk,a,b,c,r:
instd_logic;
a_out,b_out,c_out,r_out:
outstd_logic）;
endcomponent;
componentlockis
port（clk,a,b,c,reset:
instd_logic;
alarm,unlock:
outstd_logic;
y:
outstd_logic_vector（3downto0））;
endcomponent;
componentseq7is
port（a:
instd_logic_vector（3downto0）;
led:
outstd_logic_vector（6downto0））;
endcomponent;
componentfengmingis
port（larm,clk:
instd_logic;
b,c:
outstd_logic）;
endcomponent;
signalaa,bb,cc,rr,out_a,out_b,out_c,out_r,out_alarm:
std_logic;
signalout_y:
std_logic_vector（3downto0）;
begin
u1:
qudouportmap（clk,aa,bb,cc,rr,out_a,out_b,out_c,out_r）;
u2:
lockportmap（clk,out_a,out_b,out_c,out_r,out_alarm,unlock,out_y）;
u3:
seq7portmap（out_y,led）;
u4:
fengmingportmap（out_alarm,clk,f,alarm）;
u5:
fanportmap（a,b,c,r,aa,bb,cc,rr）;
endarchitecturea;
libraryieee;
useieee.std_logic_1164.all;
entityqudouis
port（a,b,c,r,clk:
instd_logic;
a_out,b_out,c_out,r_out:
outstd_logic）;
endentityqudou;
architecturedttofqudouis
signald0,d1,m0,m1,n0,n1,p0,p1:
std_logic;
begin
process（clk）
begin
if（clk'eventandclk='1'）then
d0<=nota;
d1<=d0;
m0<=notb;
m1<=m0;
n0<=notc;
n1<=n0;
p0<=notr;
p1<=p0;
endif;
endprocess;
a_out<=d1andnotd0;
b_out<=m1andnotm0;
c_out<=n1andnotn0;
r_out<=p1andnotp0;
endarchitecturedtt;
libraryieee;
useieee.std_logic_1164.all;
entitylockis
port（clk,a,b,c,reset:
instd_logic;
alarm,unlock:
outstd_logic;
y:
outstd_logic_vector（3downto0））;
endentitylock;
architecturebehaviouroflockis
typestate_typeis（s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11）;
signalpresent_state,next_state:
state_type;
begin
seq:
process（clk）is
begin
if（clk'eventandclk='1'）then
present_state<=next_state;
endif;
endprocess;
com:
process（reset,a,b,c,present_state）is
begin
alarm<='1';unlock<='1';y<="0000";
casepresent_stateis
whens0=>
alarm<='1';unlock<='1';y<="0000";
if（reset='1'）then
next_state<=s0;
elsif（b='1'）then
next_state<=s1;
elsif（a='1'orc='1'）then
next_state<=s3;
elsenext_state<=s0;
endif;
whens1=>
alarm<='1';unlock<='1';y<="0001";
if（reset='1'）then
next_state<=s0;
elsif（a='1'）then
next_state<=s4;
elsif（b='1'）then
next_state<=s5;
elsif（c='1'）then
next_state<=s6;
elsenext_state<=s1;
endif;
whens2=>
alarm<='0';unlock<='1';y<="0010";
if（reset='1'）then
next_state<=s11;
elsif（a='1'）then
next_state<=s0;
elsif（b='1'）then
next_state<=s11;
elsif（c='1'）then
next_state<=s2;
elsenext_state<=s2;
endif;
whens3=>
alarm<='1';unlock<='1';y<="0011";
if（reset='1'）then
next_state<=s0;
elsif（a='1'）then
next_state<=s4;
elsif（b='1'orc='1'）then
next_state<=s5;
elsenext_state<=s3;
endif;
whens4=>
alarm<='1';unlock<='1';y<="0100";
if（reset='1'ora='1'）then
next_state<=s0;
elsif（b='1'orc='1'）then
next_state<=s9;
elsenext_state<=s4;
endif;
whens5=>
alarm<='1';unlock<='1';y<="0101";
if（reset='1'）then
next_state<=s0;
elsif（a='1'）then
next_state<=s7;
elsif（b='1'orc='1'）then
next_state<=s9;
elsenext_state<=s5;
endif;
whens6=>
alarm<='1';unlock<='1';y<="0110";
if（reset='1'）then
next_state<=s0;
elsif（a='1'）then
next_state<=s8;
elsif（b='1'orc='1'）then
next_state<=s9;
elsenext_state<=s6;
endif;
whens7=>
alarm<='1';unlock<='1';y<="0111";
if（reset='1'ora='1'）then
next_state<=s0;
elsif（b='1'orc='1'）then
next_state<=s11;
elsenext_state<=s7;
endif;
whens8=>
alarm<='1';unlock<='1';y<="1000";
if（reset='1'ora='1'）then
next_state<=s0;
elsif（b='1'）then
next_state<=s11;
elsif（c='1'）then
next_state<=s10;
elsenext_state<=s8;
endif;
whens9=>
alarm<='1';unlock<='1';y<="1001";
if（reset='1'）then
next_state<=s0;
elsif（a='1'orb='1'orc='1'）then
next_state<=s11;
elsenext_state<=s9;
endif;
whens10=>
alarm<='1';unlock<='0';y<="1010";
if（reset='1'ora='1'orb='1'orc='1'）then
next_state<=s0;
elsenext_state<=s10;
endif;
whens11=>
alarm<='0';unlock<='1';y<="1011";
if（reset='1'ora='1'orb='1'）then
next_state<=s11;
elsif（c='1'）then
next_state<=s2;
else
next_state<=s11;
endif;
endcase;
endprocesscom;
endarchitecturebehaviour;
libraryieee;
useieee.std_logic_1164.all;
entityseq7is
port（a:
instd_logic_vector（3downto0）;
led:
outstd_logic_vector（6downto0））;
endseq7;
architectureseq7_behaveofseq7is
signalsel:
std_logic_vector（3downto0）;
begin
sel（0）<=a（0）;
sel
（1）<=a
（1）;
sel
（2）<=a
（2）;
sel（3）<=a（3）;
withselselect
led<="0001110"when"0000",--L
"0110000"when"0001",
"1101101"when"0010",
"1111001"when"0011",
"0110011"when"0100",
"1011011"when"0101",
"1011111"when"0110",
"1110000"when"0111",
"1111111"when"1000",
"1111011"when"1001",
"0111110"when"1010",--U
"1110111"when"1011",--A
"0000000"whenothers;
endseq7_behave;
libraryieee;
useieee.std_logic_1164.all;
entityfengmingis
port（larm,clk:
instd_logic;
b,c:
outstd_logic）;
endentity;
architecturefengoffengmingis
begin
b<=clkandnotlarm;
c<=larm;
endarchitecture;
libraryieee;--fan
useieee.std_logic_1164.all;
entityfanis
port（a,b,c,d:
INstd_logic;
aa,bb,cc,dd:
outstd_logic）;
endentityfan;
architecturefan_arcoffanis
begin
aa<=nota;
bb<=notb;
cc<=notc;
dd<=notd;
endfan_arc;
Circuitmap
六、实验结果与实验处理
Timingdiagram
a-b-c-candalarm
c-aandbacktothelockstate
b-c-a-candunlock
Thefunctionofristoreset
六、讨论与结论
1.Thisprogramisverycomplexandincludelotsofthings,andwemustknownthefunctiondeeplyandthentranslateitintoprogramlanguage,soitisquitedifficultforus.
2.Whendesigningtheprogram,weshoulddrawthestatemachineofadigitallockatfirst,andthensetdifferentinputs,outputsandsignalsaccordingtothestatemachine.
3.Thereare5inputs:
a,b,c,randclock.Ifweclicka-b-c-c,thealarmwillring.Ifwewanttoopenthedigitallock,theonlywayistoclickb-c-a-c.Whenalarmringing,wecouldclickc-atostopit.
4.InthisexperimentIcanuseQuartersII5.0proficiently,suchashowtodesigntheprogramandhowtofindouttheerrorsandsolutetheproblem.
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