VHDL数字锁实验报告英文版.docx

1、VHDL数字锁实验报告英文版 VHDL与数字系统设计课程设计报告名 称： VHDL与数字系统设计 题 目： 数字锁 院 系： 班 级： 学 号： 学生姓名： 指导教师： 成 绩： 日期： 年 月 日一、实验目的1. To design a finite state machine for a digital lock. 2. To learn to use HDL or the State Editor to define a finite state machine. 3. To implement the finite state machine of the digital lock o

2、n a FPGA or CPLD 4. Learn practical issues related to timing and testing of a synchronous FSM: generating a single synchronous input pulse when pressing a push-button synchronization of inputs.5. To experimentally check the operation of the lock.二、实验类型Synthesis and Design三、实验仪器Computer with the soft

3、ware Quartus II 5.0, Experimental box四、实验原理It is a complex design. You need to use all your knowledge about VHDL to complete the design. (一) You need to design a digital lock that has three input push-buttons: A, B and C. Assume that the buttons cannot be pressed simultaneously (an electromechanical

4、 interlock guarantees this). The lock should have the following features: 1. When the combination B-C-A-C has been pressed, a signal UNLOCK is asserted that causes the lock to open. 2. Once the lock is open, one can close the lock by pressing any key. 3. To reset the lock to its initial state one ca

5、n press the sequence A-A from any state, except the alarm state or the reset state. 4. In order to prevent tampering with the lock, an ALARM will go off after pressing a wrong button. However, in order to make it harder to figure out the right sequence, we dont want the alarm to go off after the fir

6、st wrong button has been pressed. Instead, the alarm should go off after pressing 4 buttons, as long as one of the 4 buttons pressed is a wrong one (e.g. the sequences B-C-B-A, A-B-C-A, C-C-B-A, A-A-B-C, etc. would trigger the alarm). 5. The only way to get out of the alarm state is by pressing the

7、C-A sequence. Use as few states as possible without compromising the operation or security of the lock. The project involves a considerable design component as well as implementation issues. In order to give yourself enough time to debug and implement the digital lock, you should start early and do

8、most of the design work during the pre-lab.（二）the state machine is:present_stateconditionnext_stateOut_putS0(LOCK RESET)RS0U:0A:0X:0000BS1A 或 CS3S1(B)RS0U:0A:0X:0001CS6AS4BS5S2(alarm+C)R OR BS11U:0 A:1X:0010AS4CS2S3(C,A)RS0U:0A:0X:0011AS4B OR CS9S4(AA,BA,CA)AS0U:0 A:0X:0100B OR CS8S5(AC,AB,BB,CB,CC)

9、A OR RS0U:0 A:0X:0101B OR CS9S6(BC)RS0U:0 A:0X:0110AS8B OR CS9S7(ABA,ACA,BBA,CBA,CCA)A OR RS0U:0 A:0X:0111B OR CS11S8(BCA)A OR RS0U:0 A:0X:1000CS10BS11S9(其他三位数)RS0U:0 A:0 X:1001A OR B OR CS11S10(unlock BCAC)R OR A OR C OR BS0U:1 A：0 X：1010S11（ALARM）CS2A：1 U：0X:1011R OR A OR BS11五、实验内容The design usin

10、g VHDL language:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity digital_lock is port(a,b,c,r:in std_logic; clk:in std_logic; alarm,unlock,f:out std_logic; led:out std_logic_vector(6 downto 0);end entity digital_lock;architecture a of digit

11、al_lock is component fan is port(a,b,c,d: IN std_logic; aa,bb,cc,dd: out std_logic); end component; component qudou is port(clk,a,b,c,r:in std_logic; a_out,b_out,c_out,r_out:out std_logic); end component; component lock is port(clk,a,b,c,reset: in std_logic; alarm,unlock: out std_logic; y: out std_l

12、ogic_vector(3 downto 0); end component; component seq7 is port(a:in std_logic_vector(3 downto 0); led:out std_logic_vector(6 downto 0); end component; component fengming is port(larm,clk: in std_logic; b,c:out std_logic); end component;signal aa,bb,cc,rr,out_a,out_b,out_c,out_r,out_alarm:std_logic;

13、signal out_y:std_logic_vector(3 downto 0);begin u1:qudou port map(clk,aa,bb,cc,rr,out_a,out_b,out_c,out_r); u2:lock port map(clk,out_a,out_b,out_c,out_r,out_alarm,unlock,out_y); u3:seq7 port map(out_y,led); u4:fengming port map(out_alarm,clk,f,alarm); u5:fan port map(a,b,c,r,aa,bb,cc,rr);end archite

14、cture a;library ieee;use ieee.std_logic_1164.all;entity qudou is port(a,b,c,r,clk:in std_logic; a_out,b_out,c_out,r_out:out std_logic);end entity qudou;architecture dtt of qudou is signal d0,d1,m0,m1,n0,n1,p0,p1:std_logic; begin process(clk) begin if(clkevent and clk=1)then d0=not a; d1=d0; m0=not b

15、; m1=m0; n0=not c; n1=n0; p0=not r; p1=p0; end if; end process; a_out=d1 and not d0; b_out=m1 and not m0; c_out=n1 and not n0; r_out=p1 and not p0;end architecture dtt;library ieee;use ieee.std_logic_1164.all;entity lock is port(clk,a,b,c,reset: in std_logic; alarm,unlock: out std_logic; y: out std_

16、logic_vector(3 downto 0);end entity lock;architecture behaviour of lock is type state_type is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11); signal present_state,next_state:state_type; begin seq:process(clk) is begin if(clkevent and clk=1)then present_state=next_state; end if; end process ; com:process(re

17、set,a,b,c,present_state) is begin alarm=1;unlock=1;y alarm=1;unlock=1;y=0000; if(reset=1)then next_state=s0; elsif(b=1)then next_state=s1; elsif(a=1 or c=1) then next_state=s3; else next_state alarm=1;unlock=1;y=0001; if(reset=1)then next_state=s0; elsif(a=1)then next_state=s4; elsif(b=1)then next_s

18、tate=s5; elsif(c=1)then next_state=s6; else next_state alarm=0;unlock=1;y=0010; if(reset=1)then next_state=s11; elsif(a=1)then next_state=s0; elsif(b=1)then next_state=s11; elsif(c=1)then next_state=s2; else next_state alarm=1;unlock=1;y=0011; if(reset=1)then next_state=s0; elsif(a=1)then next_state

19、=s4; elsif(b=1 or c=1) then next_state=s5; else next_state alarm=1;unlock=1;y=0100; if(reset=1 or a=1)then next_state=s0; elsif(b=1 or c=1) then next_state=s9; else next_state alarm=1;unlock=1;y=0101; if(reset=1)then next_state=s0; elsif(a=1)then next_state=s7; elsif(b=1 or c=1) then next_state=s9;

20、else next_state alarm=1;unlock=1;y=0110; if(reset=1)then next_state=s0; elsif(a=1)then next_state=s8; elsif(b=1 or c=1) then next_state=s9; else next_state alarm=1;unlock=1;y=0111; if(reset=1 or a=1)then next_state=s0; elsif(b=1 or c=1) then next_state=s11; else next_state alarm=1;unlock=1;y=1000; i

21、f(reset=1 or a=1)then next_state=s0; elsif(b=1) then next_state=s11; elsif(c=1)then next_state=s10; else next_state alarm=1;unlock=1;y=1001; if(reset=1)then next_state=s0; elsif(a=1 or b=1 or c=1) then next_state=s11; else next_state alarm=1;unlock=0;y=1010; if(reset=1 or a=1 or b=1 or c=1)then next

22、_state=s0; else next_state alarm=0;unlock=1;y=1011; if(reset=1 or a=1 or b=1)then next_state=s11; elsif(c=1)then next_state=s2; else next_state=s11; end if; end case; end process com; end architecture behaviour;library ieee;use ieee.std_logic_1164.all;entity seq7 is port (a:in std_logic_vector(3 dow

23、nto 0); led:out std_logic_vector(6 downto 0);end seq7;architecture seq7_behave of seq7 issignal sel : std_logic_vector(3 downto 0);begin sel(0) =a(0); sel(1) =a(1); sel(2) =a(2); sel(3) =a(3); with sel select led=0001110 when 0000, -L 0110000 when 0001, 1101101 when 0010, 1111001 when 0011, 0110011

24、when 0100, 1011011 when 0101, 1011111 when 0110, 1110000 when 0111, 1111111 when 1000, 1111011 when 1001, 0111110 when 1010, -U 1110111 when 1011, -A 0000000 when others;end seq7_behave; library ieee;use ieee.std_logic_1164.all;entity fengming is port(larm,clk: in std_logic; b,c:out std_logic);end e

25、ntity;architecture feng of fengming is begin b=clk and not larm; c=larm;end architecture;library ieee; -fanuse ieee.std_logic_1164.all;entity fan isport (a,b,c,d: IN std_logic; aa,bb,cc,dd: out std_logic);end entity fan;architecture fan_arc of fan isbegin aa=not a;bb=not b;cc=not c;dd=not d;end fan_

26、arc; Circuit map 六、实验结果与实验处理Timing diagrama-b-c-c and alarmc-a and back to the lock stateb-c-a-c and unlockThe function of r is to reset六、讨论与结论1. This program is very complex and include lots of things , and we must known the function deeply and then translate it into program language , so it is qui

27、te difficult for us.2. When designing the program ,we should draw the state machine of a digital lock at first, and then set different inputs,outputs and signals according to the state machine.3. There are 5 inputs :a,b,c,r and clock.If we click a-b-c-c, the alarm will ring. If we want to open the digital lock ,the only way is to click b-c-a-c.When alarm ringing ,we could click c-a to stop it. 4. In this experiment I can use Quarters II 5.0 proficiently , such as how to design the program and how to find out the errors and solute the problem.