EDA题目.docx
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EDA题目
现场设计参考题目
1、采用文本编辑法，利用VHDL语言实现1位全加器的设计（并行布尔方程法）
--并行布尔方程法
libraryieee;
useieee.std_logic_1164.all;
entityAdderFullis
port（ai,bi,ci_1:
instd_logic;
si,ci:
outstd_logic）;
endAdderFull;
architectureArcAdderFullofAdderFullis
begin
si<=aixorbixorci_1;
ci<=（aiandbi）or（aiandci_1）or（biandci_1）;
endArcAdderFull;
--AdderFull_2.vhdl
2、采用文本编辑法，利用VHDL语言实现1位全加器的设计（并行withselectwhen方法）
libraryieee;
useieee.std_logic_1164.all;
entityAdderFull_2is
port（ai,bi,ci_1:
instd_logic;
si,ci:
outstd_logic）;
endAdderFull_2;
architectureArcAdderFull_2ofAdderFull_2is
signalinstruction:
std_logic_vector（2downto0）;
begin
instruction<=ci_1&bi&ai;
withinstructionselect
si<='0'when"000",
'1'when"001",
'1'when"010",
'0'when"011",
'1'when"100",
'0'when"101",
'0'when"110",
'1'when"111",
'Z'whenothers;
withinstructionselect
ci<='0'when"000",
'0'when"001",
'0'when"010",
'1'when"011",
'0'when"100",
'1'when"101",
'1'when"110",
'1'when"111",
'Z'whenothers;
endArcAdderFull_2;
--AdderFull_3.vhd
3、采用文本编辑法，利用VHDL语言实现1位全加器的设计（并行whenelse方法）
libraryieee;
useieee.std_logic_1164.all;
entityAdderFull_3is
port（ai,bi,ci_1:
instd_logic;
si,ci:
outstd_logic）;
endAdderFull_3;
architectureArcAdderFull_3ofAdderFull_3is
signalinGroup:
std_logic_vector（2downto0）;
signaloutGroup:
std_logic_vector（1downto0）;
begin
inGroup<=ci_1&bi&ai;
outGroup<="00"wheninGroup="000"else
"01"wheninGroup="001"else
"01"wheninGroup="010"else
"10"wheninGroup="011"else
"01"wheninGroup="100"else
"10"wheninGroup="101"else
"10"wheninGroup="110"else
"11"wheninGroup="111"else
"ZZ";
process（outGroup）
begin
ci<=outGroup
（1）;
si<=outGroup（0）;
endprocess;
endArcAdderFull_3;
--AdderFull_4.vhd
4、利用VHDL语言实现1位全加器的设计（进程顺序语句ifthenelse真值表法）
libraryieee;
useieee.std_logic_1164.all;
entityAdderFull_4is
port（ci_1,bi,ai:
instd_logic;
ci,si:
outstd_logic）;
endAdderFull_4;
architectureArcAdderFull_4ofAdderFull_4is
signalinGroup:
std_logic_vector（2downto0）;
begin
inGroup<=ci_1&bi&ai;
process（inGroup）
variableoutGroup:
std_logic_vector（1downto0）;
begin
if（inGroup="000"）thenoutGroup:
="00";
elsif（inGroup="001"）thenoutGroup:
="01";
elsif（inGroup="010"）thenoutGroup:
="01";
elsif（inGroup="011"）thenoutGroup:
="10";
elsif（inGroup="100"）thenoutGroup:
="01";
elsif（inGroup="101"）thenoutGroup:
="10";
elsif（inGroup="110"）thenoutGroup:
="10";
elsif（inGroup="111"）thenoutGroup:
="11";
elseoutGroup:
="ZZ";
endif;
ci<=outGroup
（1）;
si<=outGroup（0）;
endprocess;
endArcAdderFull_4;
5、利用VHDL语言实现1位全加器的设计（进程顺序语句casewhen真值表法）
libraryieee;
useieee.std_logic_1164.all;
entityAdderFull_5is
port（ci_1,bi,ai:
instd_logic;
ci,si:
outstd_logic）;
endAdderFull_5;
architectureArcAdderFull_5ofAdderFull_5is
signalinGroup:
std_logic_vector（2downto0）;
begin
inGroup<=ci_1&bi&ai;
process（inGroup）
variableoutGroup:
std_logic_vector（1downto0）;
begin
caseinGroupis
when"000"=>outGroup:
="00";
when"001"=>outGroup:
="01";
when"010"=>outGroup:
="01";
when"011"=>outGroup:
="10";
when"100"=>outGroup:
="01";
when"101"=>outGroup:
="10";
when"110"=>outGroup:
="10";
when"111"=>outGroup:
="11";
whenothers=>outGroup:
="ZZ";
endcase;
ci<=outGroup
（1）;
si<=outGroup（0）;
endprocess;
endArcAdderFull_5;
6、采用文本编辑法，利用VHDL语言实现RS触发器的设计
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityRSis
port（s,r:
instd_logic;
q,qn:
outstd_logic）;
end;
architectureoneofRSis
signalq1,qn1:
std_logic;
begin
q1<=snandqn1;
qn1<=rnandq1;
q<=q1;
qn<=qn1;
end;
7、采用文本编辑法，利用VHDL语言实现D触发器的设计
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydis
port（d,cp,r,s:
instd_logic;
q,qn:
outstd_logic）;
end;
architectureoneofdis
signalq_temp,qn_temp:
std_logic;
begin
process（cp,r,s,q_temp,qn_temp）
begin
ifr='0'ands='1'then
q_temp<='0';
qn_temp<='1';
elsifr='1'ands='0'then
q_temp<='1';
qn_temp<='0';
elsifr='0'ands='0'then
q_temp<=q_temp;
qn_temp<=qn_temp;
elsifcp'eventandcp='1'then
q_temp<=d;
qn_temp<=notd;
endif;
endprocess;
q<=q_temp;
qn<=qn_temp;
end;
8、采用文本编辑法，利用VHDL语言实现JK触发器的设计
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityJKis
port（j,k,r,s,cp:
instd_logic;
q,qn:
outstd_logic）;
end;
architectureoneofJkis
signalq_temp,qn_temp:
std_logic;
begin
process（j,k,cp,r,s,q_temp,qn_temp）
begin
ifr='0'ands='1'then
q_temp<='0';
qn_temp<='1';
elsifr='1'ands='0'then
q_temp<='1';
qn_temp<='0';
elsifr='0'ands='0'then
q_temp<=q_temp;
qn_temp<=qn_temp;
elsifcp'eventandcp='1'then
ifj='0'andk='1'then
q_temp<='0';
qn_temp<='1';
elsifj='1'andk='0'then
q_temp<='1';
qn_temp<='0';
elsifj='1'andk='1'then
q_temp<=notq_temp;
qn_temp<=notqn_temp;
endif;
endif;
endprocess;
q<=q_temp;
qn<=qn_temp;
end;
9、采用文本编辑法，利用VHDL语言实现二输入与非门的设计
libraryieee;
useieee.std_logic_1164.all;
entitynand_2_1is
port（a,b:
instd_logic;
y:
outstd_logic）;
end;
architectureoneofnand_2_1is
signalab:
std_logic_vector（1downto0）;
begin
ab<=a&b;
process（ab）is
begin
caseabis
when"00"=>y<='1';
when"01"=>y<='1';
when"10"=>y<='1';
when"11"=>y<='0';
whenothers=>null;
endcase;
endprocess;
end;
10、采用文本编辑法，利用VHDL语言实现二输入或非门的设计
libraryieee;
useieee.std_logic_1164.all;
entitynor_2_1is
port（a,b:
instd_logic;
y:
outstd_logic）;
end;
architectureoneofnor_2_1is
signalab:
std_logic_vector（1downto0）;
begin
ab<=a&b;
process（ab）is
begin
caseabis
when"00"=>y<='1';
when"01"=>y<='0';
when"10"=>y<='0';
when"11"=>y<='0';
whenothers=>null;
endcase;
endprocess;
end;
11、采用文本编辑法，利用VHDL语言实现二输入异或门的设计
libraryieee;
useieee.std_logic_1164.all;
entityor2is
port（a,b:
instd_logic;
c:
outstd_logic）;
end;
architectureoneofor2is
begin
c<=aorb;
end;
12、采用文本编辑法，利用VHDL语言实现三态缓冲门的设计
libraryieee;
useieee.std_logic_1164.all;
entitytri_gateis
port（din,en:
instd_logic;
dout:
outstd_logic）;
end;
architectureoneoftri_gateis
begin
dout<=dinwhenen='1'else'Z';
end;
13、采用文本编辑法，利用VHDL语言实现单向总线（8位）缓冲器的设计
libraryieee;
useieee.std_logic_1164.all;
entitytri_bufferis
port（din:
instd_logic_vector（7downto0）;
en:
instd_logic;
dout:
outstd_logic_vector（7downto0））;
end;
architectureoneoftri_bufferis
begin
process（en,din）
begin
ifen='1'thendout<=din;
elsedout<="ZZZZZZZZ";
endif;
endprocess;
end;
15、采用文本编辑法，利用VHDL语言实现双向总线（8位）缓冲器的设计
libraryieee;
useieee.std_logic_1164.all;
entitytri_bibufferis
port（a,b:
inoutstd_logic_vector（7downto0）;
en:
instd_logic;
dr:
instd_logic）;
end;
architectureoneoftri_bibufferis
signala_out,b_out:
std_logic_vector（7downto0）;
begin
process（a,b_out,en,dr）
begin
ifen='1'anddr='1'thenb_out<=a;
elseb_out<="ZZZZZZZZ";
endif;
b<=b_out;
endprocess;
process（a_out,b,en,dr）
begin
ifen='1'anddr='0'thena_out<=b;
elsea_out<="ZZZZZZZZ";
endif;
a<=a_out;
endprocess;
end;
16、采用文本编辑法，利用VHDL语言实现同步4位二进制加法计数器设计
libraryieee;
useieee.std_logic_1164.all;
entitybcd_decoderis
port（i:
instd_logic_vector（3downto0）;
y:
outstd_logic_vector（7downto0））;
end;
architectureoneofbcd_decoderis
begin
process（i）
begin
caseiis
when"0000"=>y<="11111100";
when"0001"=>y<="01100000";
when"0010"=>y<="11011010";
when"0011"=>y<="11110010";
when"0100"=>y<="01100110";
when"0101"=>y<="10110110";
when"0110"=>y<="10111110";
when"0111"=>y<="11100000";
when"1000"=>y<="11111110";
when"1001"=>y<="11110110";
when"1010"=>y<="11101110";
when"1011"=>y<="00111110";
when"1100"=>y<="10011100";
when"1101"=>y<="01111010";
when"1110"=>y<="10011110";
when"1111"=>y<="10001110";
whenothers=>y<="11111111";
endcase;
endprocess;
end;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt4is
port（clk:
instd_logic;
rst:
instd_logic;
en:
instd_logic;
q:
outstd_logic_vector（3downto0））;
end;
architectureoneofcnt4is
signalq1:
std_logic_vector（3downto0）;
begin
Process（clk,en,rst）
begin
ifen='1'then
ifrst='1'thenq1<="0000";
elsifclk'eventandclk='1'then
q1<=q1+1;
endif;
endif;
endprocess;
q<=q1;
end;
17、采用文本编辑法，利用VHDL语言实现四选一数据选择器的设计
libraryieee;
useieee.std_logic_1164.all;
entitymux4is
port（d0,d1,d2,d3:
instd_logic;
g:
instd_logic;
a:
instd_logic_vector（1downto0）;
y:
outstd_logic）;
end;
architectureoneofmux4is
begin
process（a,g,d0,d1,d2,d3）
begin
ifg='0'theny<='0';
else
caseais
when"00"=>y<=d0;
when"01"=>y<=d1;
when"10"=>y<=d2;
when"11"=>y<=d3;
whenothers=>y<='0';
endcase;
endif;
endprocess;
end;
18、采用文本编辑法，利用VHDL语言实现八选一数据选择器的设计
libraryieee;
useieee.std_logic_1164.all;
entitymux8is
port（d0,d1,d2,d3,d4,d5,d6,d7:
instd_logic;
g:
instd_logic;
a:
instd_logic_vector（2downto0）;
y:
outstd_logic）;
end;
architectureoneofmux8is
begin
process（a,g,d0,d1,d2,d3,d4,d5,d6,d7）
begin
ifg='0'theny<='0';
else
caseais
when"000"=>y<=d0;
when"001"=>y<=d1;
when"010"=>y<=d2;
when"011"=>y<=d3;
when"100"=>y<=d4;
when"101"=>y<=d5;
when"110"=>y<=d6;
when"111"=>y<=d7;
whenothers=>y<='0';
endcase;
endif;
endprocess;
end;
19、采用文本编辑法，利用VHDL语言实现同步10进制加法计数器设计
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycountis
port（clk,reset:
instd_logic;
cnt:
outintegerrange0to10）;
endentity;
architectureartofco
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