at89c51单片机外文资料.docx

1、at89c51单片机外文资料AT89C51的介绍（原文出处：http：89C89C89C89C89C89C89CThe device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a

2、conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides

3、 the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down

4、 to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip fun

5、ctions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance 0 may also be configured to

6、 be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during programverification.Port

7、 1Port 1 is an 8-bit bi-directional I/O port with internal Port 1 output buffers can sink/source four TTL 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because

8、 of the internal 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal Port 2 output buffers can sink/source four TTL 1s are written to Port 2 pins they are pulled high by the internal pullups and can be u

9、sed as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses s

10、trong internal pullupswhen emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-di

11、rectional I/O port with internal Port 3 output buffers can sink/source four TTL 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the 3 also serves the

12、functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse

13、for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that

14、one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no eff

15、ect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external

16、 data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on should be strapped to VCC for inte

17、rnal program pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator Cha

18、racteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconne

19、cted while XTAL1 is driven as shown in Figure are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Figure 1. Osci

20、llator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode

21、. The idle mode can be terminated by any enabled interrupt or by a hardware should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip har

22、dware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to

23、 external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down i

24、s a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three

25、lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a

26、random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Synthesis of an 8051-Like Micro-Controller Tolerant to Transient FaultsThis paper presents t

27、he implementation of a fault detection and correction technique used to design a robust 8051 micro-controller with respect to a particular transient fault called Single Event Upset (SEU). A specific study regarding the effects of a SEU in the micro-controller behavior was performed. Furthermore, a f

28、ault tolerant technique was implemented in a version of the 8051. The VHDL description of the fault-tolerant microprocessor was prototyped in a FPGA environment and results in terms of area overhead, level of protection and performance penalties are discussed.1. IntroductionThe constant improvements

29、 achieved in the microelectronics technology allow the manufacturing of very complex circuits, substituting boards or even computers of the past 80s. Nowadays, because of the microelectronics advances, traditional applications become cheaper and more reliable, while a large range of new applications

30、 can take advantage of integrated devices by using the so-called embedded systems. In all cases, architectures are strongly based on some kind of data processor, such as a micro-controller or a DSP processing unit, for example. The continuous decrease in the semiconductor dimensions and in electrica

31、l features, leads to an increasing sensitivity to some effects of the environment (ionization due to radiation, magnetic perturbations, thermal,.) considered minor or negligible in the technologies of the past. Particularly, digital circuits operating in space are subject to different kinds of radia

32、tion. However, some problems have also been reported for some Earth applications, like avionics systems .Radiation effects can be permanent or transient . Permanent faults result from particles trapped at the silicon/oxide interfaces and appear only after long exposure to radiation (Total Ionization Dose). Transient faults (Single Event Effects, SEE) may be caused by the impact