基于FPGA的数字系统设计实验3lcd显示字符OK的程序.docx

1、基于FPGA的数字系统设计实验3lcd显示字符OK的程序timescale 1ns / 1ps/ Company: / Engineer: / / Create Date: 15:48:30 04/21/2015 / Design Name: / Module Name: lcd / Project Name: / Target Devices: / Tool versions: / Description: / Dependencies: / Revision: / Revision 0.01 - File Created/ Additional Comments: /module lcd(

2、clk,reset,lcd_rs,lcd_rw,lcd_e,lcd_d,flash_ce); input clk; input reset; output lcd_rs; output lcd_rw; output lcd_e; output 3:0 lcd_d; output flash_ce; reg lcd_rs,lcd_e; reg3:0 lcd_d; assign flash_ce = 1; assign lcd_rw = 0; reg 19:0 delay_count; reg 19:0 num_count; parameter state1 = 6b000001; paramet

3、er state2 = 6b000010; parameter state3 = 6b000011; parameter state4 = 6b000100; parameter state5 = 6b000101; parameter state6 = 6b000110; parameter state7 = 6b000111; parameter state8 = 6b001000; parameter state9 = 6b001001; parameter state10 = 6b001010; parameter state11 = 6b001011; parameter state

4、12 = 6b001100; parameter state13 = 6b001101; parameter state14 = 6b001110; parameter state15 = 6b001111; parameter state16 = 6b010000; parameter state17 = 6b010001; parameter state18 = 6b010010; parameter state19 = 6b010011; parameter state20 = 6b010100; parameter state21 = 6b010101; parameter state

5、22 = 6b010110; parameter state23 = 6b010111; parameter state24 = 6b011000; parameter state25 = 6b011001; parameter state26 = 6b011010; parameter state27 = 6b011011; parameter state28 = 6b011100; parameter state29 = 6b011101; parameter state30 = 6b011110; parameter state31 = 6b011111; parameter state

6、32 = 6b100000; parameter state33 = 6b100001; parameter state34 = 6b100010; parameter state35 = 6b100011; parameter state36 = 6b100100; parameter state37 = 6b100101; parameter state38 = 6b100110; parameter state39 = 6b100111; parameter state40 = 6b101000; parameter state41 = 6b101001; parameter state

7、42 = 6b101010; parameter state43 = 6b101011; parameter state44 = 6b101100; parameter state45 = 6b101101; parameter state46 = 6b101110; parameter state47 = 6b101111; parameter state48 = 6b110000; parameter state49 = 6b110001; parameter state50 = 6b110010; parameter state51 = 6b110011; parameter state

8、52 = 6b110100; parameter state53 = 6b110101; parameter state54 = 6b110110; parameter state55 = 6b110111; parameter state56 = 6b111000; parameter state57 = 6b111001; parameter state58 = 6b111010; parameter state59 = 6b111011; reg 5:0 state; reg state_change; always (posedge clk or posedge reset) if(r

9、eset) begin state_change = 1b0; delay_count = 1b1; end else if(delay_count = num_count - 1) begin state_change = 1b1; delay_count = 1b1; end else begin state_change = 1b0; delay_count = delay_count + 1b1; end always (posedge state_change or posedge reset) if(reset) begin state = state1; num_count =

10、20d750000; end else case(state) state1:begin state = state2; num_count = 20d4; lcd_rs = 1b0; lcd_e = 1b0; lcd_d = 4h3; end state2:begin state = state3; num_count = 20d12; lcd_e = 1b1; end state3:begin state = state4; num_count = 20d205000; lcd_e = 1b0; end state4:begin state = state5; num_count = 20

11、d4; lcd_d = 4h3; end state5:begin state = state6; num_count = 20d12; lcd_e = 1b1; end state6:begin state = state7; num_count = 20d5000; lcd_e = 1b0; end state7:begin state = state8; num_count = 20d4; lcd_d = 4h2; end state8:begin state = state9; num_count = 20d12; lcd_e = 1b1; end state9:begin state

12、 = state10; num_count = 20d4000; lcd_e = 1b0; end /set funtion mode state10:begin state = state11; num_count = 20d4; lcd_rs = 0; lcd_d = 4h2; end state11:begin state = state12; num_count = 20d12; lcd_e = 1b1; end state12:begin state = state13; num_count = 20d80; lcd_e = 1b0; end state13:begin state

13、= state14; num_count = 20d4; lcd_d = 4h8; end state14:begin state = state15; num_count = 20d12; lcd_e = 1b1; end state15:begin state = state16; num_count = 20d4000; lcd_e = 1b0; end /set entry mode state16:begin state = state17; num_count = 20d4; lcd_d = 4h0; end state17:begin state = state18; num_c

14、ount = 20d12; lcd_e = 1b1; end state18:begin state = state19; num_count = 20d80; lcd_e = 1b0; end state19:begin state = state20; num_count = 20d4; lcd_d = 4h6; end state20:begin state = state21; num_count = 20d12; lcd_e = 1b1; end state21:begin state = state22; num_count = 20d4000; lcd_e = 1b0; end

15、/set display on/off state22:begin state = state23; num_count = 20d4; lcd_d = 4h0; end state23:begin state = state24; num_count = 20d12; lcd_e = 1b1; end state24:begin state = state25; num_count = 20d80; lcd_e = 1b0; end state25:begin state = state26; num_count = 20d4; lcd_d = 4hc; end state26:begin

16、state = state27; num_count = 20d12; lcd_e = 1b1; end state27:begin state = state28; num_count = 20d4000; lcd_e = 1b0; end /clear display state28:begin state = state29; num_count = 20d4; lcd_d = 4h0; end state29:begin state = state30; num_count = 20d12; lcd_e = 1b1; end state30:begin state = state31;

17、 num_count = 20d80; lcd_e = 1b0; end state31:begin state = state32; num_count = 20d4; lcd_d = 4h1; end state32:begin state = state33; num_count = 20d12; lcd_e = 1b1; end state33:begin state = state34; num_count = 20d2000; lcd_e = 1b0; end state34:begin state = state35; num_count = 20d82000; end /set

18、 DD RAM address state35:begin state = state36; num_count = 20d4; lcd_rs = 1b0; lcd_e = 1b0; lcd_d = 4h8; end state36:begin state = state37; num_count = 20d12; lcd_e = 1b1; end state37:begin state = state38; num_count = 20d80; lcd_e = 1b0; end state38:begin state = state39; num_count = 20d4; lcd_d =

19、4h0; end state39:begin state = state40; num_count = 20d12; lcd_e = 1b1; end state40:begin state = state41; num_count = 20d4000; lcd_e = 1b0; end / now starts writing data to DD RAM state41:begin state = state42; num_count = 20d4; lcd_rs = 1b1; lcd_d = 4h4; end state42:begin state = state43; num_coun

20、t = 20d12; lcd_e = 1b1; end state43:begin state = state44; num_count = 20d80; lcd_e = 1b0; end state44:begin state = state45; num_count = 20d4; lcd_d = 4hf; end state45:begin state = state46; num_count = 20d12; lcd_e = 1b1; end state46:begin state = state47; num_count = 20d2000; lcd_e = 1b0; end sta

21、te47:begin state = state48; num_count = 20d4; lcd_rs = 1b1; lcd_d = 4h4; end state48:begin state = state49; num_count = 20d12; lcd_e = 1b1; end state49:begin state = state50; num_count = 20d80; lcd_e = 1b0; end state50:begin state = state51; num_count = 20d4; lcd_d = 4hb; end state51:begin state = s

22、tate52; num_count = 20d12; lcd_e = 1b1; end state52:begin state = state53; num_count = 20d2000; lcd_e = 1b0; end state53:begin state = state54; num_count = 20d4; lcd_rs = 1b1; lcd_d = 4h2; end state54:begin state = state55; num_count = 20d12; lcd_e = 1b1; end state55:begin state = state56; num_count

23、 = 20d80; lcd_e = 1b0; end state56:begin state = state57; num_count = 20d4; lcd_d = 4h1; end state57:begin state = state58; num_count = 20d12; lcd_e = 1b1; end state58:begin state = state59; num_count = 20d4000; lcd_e = 1b0; end state59:begin state = state35; num_count = 20d800; end default:begin st

24、ate = state1; num_count = 20d800; end endcase endmoduleNET clk LOC = C9 | IOSTANDARD = LVTTL ; NET flash_ce LOC = D16 | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ; NET lcd_d LOC = R15 | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ; NET lcd_d LOC = R16 | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SL

25、OW ; NET lcd_d LOC = P17 | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ; NET lcd_d LOC = M15 | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ; NET lcd_e LOC = M18 | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ; NET lcd_rs LOC = L18 | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ; NET lcd_rw LOC = L17 | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ; NET reset LOC = L13 | IOSTANDARD = LVTTL | PULLUP ;