考试B卷.docx

1、考试B卷电子科技大学2011-2012学年第 二 学期期 末 考试 B 卷课程名称：_数字逻辑设计及应用_ 考试形式： 闭卷 考试日期： 20 12 年 7 月 2 日 考试时长：_120_分钟课程成绩构成：平时 30 %， 期中 30 %， 实验 0 %， 期末 40 %本试卷试题由_六_部分构成，共_6_页。题号一二三四五六七八九十合计得分I. Fill your answers in the blanks (2 X 15=30)1. If the two adders of a 4-bit binary adder 74x283 （Figure 1.）are (1010)twos and

2、 (1101)twos, its sum is not overflow. Then its input C0 should be （ ）, its sum S3S2S1S0= ( ) twos . Figure 1.2. A circuit with 4 flip-flops can store ( ) bit binary numbers, that is, include ( ) states at most.3. If , then FD =( ), and ( ).4. A modulo-20 counter circuit needs ( ) D filp-flops at lea

3、st. A modulo-196 counter circuit needs ( ) 4-bit counters of 74x163 at least. 5. An 8-bit ring counter has ( ) normal states. If we want to realize the same number normal states, we need a ( ) bit twisted-ring counter.6. To design a 01101100 serial sequence generator by shift registers, we need a (

4、)-bit shift register as least.7. A sequential circuit whose output depends on the states and inputs is called a ( ) state machine.8. A 84 ROM stores a truth table of combinational logic function. This combinational logic function has ( ) inputs and ( ) outputs.9. The state diagram of a Moore state m

5、achine is shown as Figure 2. If the initiate state Q3Q2Q1Q0 is 1001, the output sequence of Q3 is （ ）.100100110111111111101100 Figure 2.得 分II. Please select the only one correct answer in the following questions.(2 X 5=10)1. For Johnson counter and ring counter, ( ) is correct.A. An n-bit ring count

6、er has 2n active states.B. An n-bit Johnson counter has 2n active states.C. An n-bit ring counter has 2n-2n active states.D. An n-bit Johnson counter has 2n-n active states.2. Using 4-bit synchronous binary counter 74x163 or decade counter 74x162 to design a counter from 0 to 193, ( ) is correct.A.

7、It needs at least three 74x163.B. It needs at least three 74x162.C. It needs at least two 74x162.D. It needs at least four 74x163.3. For the disposition of unused states, ( ) is not correct.A. In minimal risk, the next state of the unused state is marked as “dont-cares d”.B. Minimal risk can get a s

8、elf-correct circuit.C. Minimal cost can get a simplest circuit.D. In minimal cost, the next state of the unused state is marked as “dont-cares d”.4. If the next state of an edge-triggered J-K flip-flop is “0”, then which of following is not the possible of (J, K) ( )A. (0, 0) B. (0, 1) C. (1, 1) D.

9、(1, 0)5. There is a state/output table of a sequential machine as the table 1, what the input sequences is detected? ( )A. 11110 B. 11010 C. 10110 D. 10010SX01AA,0B,0BC,0B,0CA,0D,0DC,0E,0EC,1B,0S*,ZTable 1 得 分 .There is a logic circuit and the inputs A, B and C are corresponding to the outputs FA, F

10、B and FC .The waveforms of inputs and outputs are shown in Fig. 3. Analyze the circuit. 15(1) Fill out the truth table. 9(2) Write out the expression of the outputs FA, FB and FC. 6ABCFAFBFC000001010011100101110111ABCFAFBFC Fig. 3得 分. Analyze the clocked synchronous state machine shown in Fig. 4. 15

11、(1) Write out the excitation equations and output equation of the circuit. 5(2) Fill out the transition/output table. 10Fig. 4The transition/output table:Q2Q1XC0 100011011Q2*Q1*得 分V. Design a clock synchronous state machine with D Flip-Flops. Its state/output table is shown in Table. 2. The state as

12、signment are A: Q1Q2=00，B: Q1Q2=01，C: Q1Q2=11，D: Q1Q2=10. 15(1). Write out the transition/output table. 6(2). Write out the excitation equations and the output equation. 9 Table.2 state/output table transition/output table 得 分VI. Design a sequence signal “110010” generator only with 74x163 and 74x15

13、1. 15(1). Write out the input equation of LD_L and the load value “DCBA”. 4(2). Finish the uncompleted link lines of circuit shown in Fig. 5. 11 (Note: a. only with 74x163 and 74x151, no other gates; b. the initial state QDQCQBQA=0000)74X163的功能表输入当前状态下一状态输出CLR_LLD_LENTENPQD QC QB QAQD* QC* QB* QA*RC

14、O0XXXX X X X0 0 0 0010XXX X X XD C B A0110XX X X XQD QC QB QA011X0X X X XQD QC QB QA011110 0 0 00 0 0 1011110 0 0 10 0 1 0011110 0 1 00 0 1 1011110 0 1 10 1 0 001111.011111 1 1 10 0 0 01 74x151 的真值表 Fig. 5参考解答电子科技大学2011-2012学年第 二 学期期 末 考试 B 卷课程名称：_数字逻辑设计及应用_考试形式： 闭卷 考试日期：20 12 年 7 月 2 日 考试时长：120_分钟课

15、程成绩构成：平时 30 %， 期中 30 %， 实验 0 %， 期末 40 %本试卷试题由_六_部分构成，共_6_页。题号一二三四五六七八九十合计得分得 分I. Fill your answers in the blanks (2 X 15=30)10. If the two adders of a 4-bit binary adder 74x283 （Figure 1.）are (1010)twos and (1101)twos, its sum is not overflow, its input C0 is （ 1 ）, its sum S3S2S1S0= ( 1000 )twos .7

16、4x283C0A0B0A1B1A2B2A3B3S0S1S2S3C475632141512114113109 Figure 1.11. A circuit with 4 flip-flops can store ( 4 ) bit binary numbers, that is, include ( 16 ) states at most.12. If , then FD =( 0，2，5，6 ), and ( 0，3，4，6 ).13. A modulo-20 counter circuit needs ( 5 ) D filp-flops at least. A modulo-196 cou

17、nter circuit needs ( 2 ) 4-bit counters of 74x163 at least. 14. A 8-bit ring counter has ( 8 ) normal states. If we want to realize the same number normal states, we need a ( 4 ) bit twisted-ring counter.15. To design a 01101100 serial sequence generator by shift registers, we need a ( 5 )-bit shift

18、 register as least.16. A sequential circuit whose output depends on the states and inputs is called a ( Mealy ) state machine.17. A 84 ROM stores a truth table of combinational logic function. This combinational logic function has ( 3 ) inputs and ( 4 ) outputs.18. The state diagram of a Moore state

19、 machine is shown as Figure 2. If the initiate state Q3Q2Q1Q0 is 1001, the output sequence of Q3 is （ 100111 ）. Figure 2.得 分II. Please select the only one correct answer in the following questions.(2 X 5=10)19. 1. For Johnson counter and ring counter, ( B ) is correct.20. A. A n-bit ring counter has

20、 2n active states.21. B. A n-bit Johnson counter has 2n active states.22. C. A n-bit ring counter has 2n-2n active states.23. D.A n-bit John counter has 2n-n active states.24. 2. Using 4-bit synchronous binary counter 74x163 or decade counter 74x162 to design a counter from 0 to 193, ( B ) is correc

21、t.25. A. It needs at least three 74x163.26. B. It needs at least three 74x162.27. C. It needs at least two 74x162.28. D. It needs at least four 74x163.29. 3. For the disposition of unused states, ( A ) is not correct.30. A. In minimal risk, the next state of the unused state is marked as “dont-cares

22、 d”.31. B. Minimal risk can get a self-correct circuit.32. C. Minimal cost can get a simplest circuit.33. D. In minimal cost, the next state of the unused state is marked as “dont-cares d”.4. If the next state of an edge-triggered J-K flip-flop is “0”, then which of following is not the possible (J,

23、 K) ( D )A) (0, 0) B) (0, 1) C) (1, 1) D) (1, 0)5. There is a state/output table of a sequential machine as the table 1, what the input sequences is detected? ( C )SX01AA,0B,0BC,0B,0CA,0D,0DC,0E,0EC,1B,0S*,ZA) 11110 B) 11010 C) 10110 D) 10010Table 1 得 分III. There is a logic circuit and the inputs A,

24、 B and C are corresponding to the outputs FA, FB and FC .The waveforms of inputs and outputs are shown in Fig. 1. Analyze the circuit. 15(3) Fill out the truth table. 9(4) Write out the expression of the outputs FA, FB and FC. 6ABCFAFBFC000001010011100101110111 Fig.1 1ABCFAFBFC0000000010010100100110

25、01100100101001110010111001 FA= ABC FB= BC FC= C IV. 得 分Analyze the clocked synchronous state machine shown in Fig. 2. 15(3) Write out the excitation equations and output equation of the circuit. 5(4) Fill out the transition/output table. 10Fig. 2The transition/output table:Q2Q1XC0 100011011Q2*Q1*Q2Q

26、1XC0 1000 0 0 10010 0 1 00101 1 1 10110 0 0 11Q2*Q1*激励方程： ; ; ; ; 输出方程： V. Design a clock synchronous state machine with D Flip-Flops. Its state/output table is shown in Table. 2. The state assignment are A: Q1Q2=00，B: Q1Q2=01，C: Q1Q2=11，D: Q1Q2=10. 15(1). Write out the transition/output table. 6(2)

27、. Write out the excitation equations and the output equation. 91. 转移输出表为： Table.2 state/output table 2. 方程 VI. Design a sequence signal “110010” generator only with 74x163 and 74x151. 15(1). Write out the input equation of LD_L and the load value “DCBA”. 4(2). Finish the uncompleted link lines of circuit shown in Fig. 3. 11 (Note: a. only with 74x163 and 74x151, no other gates; b. the initial state QDQCQBQA=0000)74X163的功能表输入当前状态下一状态输出CLR_LLD_LENTENPQD QC QB QAQD* QC* QB* QA*RCO0XXXX X X X0 0 0 0010XXX X X XD C B A0110XX X X XQD QC QB QA011X0X X X XQD QC QB QA011110