DDR3 SPD 附中文翻译.docx

1、DDR3 SPD 附中文翻译Understanding DDR3 Serial Presence Detect (SPD) Table Tuesday, July 17, 2007 IntroductionSince I wrote 揢nderstanding DDR Serial Presence Detect (SPD) Table?in 2003, I have been getting a lot a feedback from readers. I added 揢nderstanding DDR2 Serial Presence Detect (SPD) Table?in 2006.

2、 Some of you told me that you are using these articles to train your employees and to introduce the mysteries SPD concept to your customers. I feel honored by your responses. Lately, CST has started shipment of a DDR3 EZ Programmer. Since the DD3 DIMM is introduced recently, I think this is the time

3、 to add an article for the DDR3 SPD Table. Due to the many more years of development, the DD3 SPD table has definitely got more sophisticated than the original DDR and DDR2 SPD table. Your attention is required to understand and follow through. I will try to use as much layman language as I can to a

4、ccommodate you all.Serial Presence Detect (SPD) data is probably the most misunderstood subject in the memory module industry. Most people only know it as the little Eeprom device on the DIMM that often kept the module from working properly in the computer. On the contrary, it is quite the opposite.

5、 The SPD data actually provide vital information to the system Bios to keep the system working in optimal condition with the memory DIMM. This article attempts to guide you through the construction of an SPD table with 揟urbo-Tax?type of multiple choices questions. I hope you抣l find it interesting an

6、d useful. Sample Jedec Standard SPD Data TableByte 0Number of Serial PD Bytes Written/ SPD Device Size/ CRC Coverage （写入的SPD字节数/EERPOM总字节数/CRC覆盖字节范围）Bit 3 to Bit 0 describes the total size of the serial memory actually used in the EEprom for the Serial Presence Detect data. Bit 6 to Bit 4 describes

7、the number of bytes available in the EEprom device, usually 128byte or 256 byte. On top of that, Bit 7 indicates whether the unique module identifier covered by the CRC encoded on bytes 126 and 127 is based on (0-116byte) or based on (0-125byte). (When CST EZ-SPD Programmer is used: Simply select it

8、ems from 3 tables and automatically calculate the final hex number)The most common one used is:Total SPD Bye = 256CRC Coverage = 0-116ByteSPD Byte used = 176 ByteResulting code is92hByte 1SPD Revision （SPD规范版本）Version 0.0 00hRevision 0.5 05hRevision 1.0 10hRevision 1.1 11hRevision 1.2 12hByte 2 （DRA

9、M类型）DRAM Device Type This refers to the DRAM type. In this case, we are only dealing with DDR3 SDRAM.DDR3 SDRAM: 0Bh Byte 3Module Type （内存module类型）This relates to the physical size, and category of memory module.Undefined 00hRDIMM (Registered Long DIMM) 01hUDIMM (Unbuffered Long DIMM) 02hSODIMM (Sma

10、ll Outline DIMM) 03hByte 4 SDRAM Density and Banks （DRAM容量和内部bank数）This byte defines the total density of the DDR3 SDRAM, in bits, and the number of internal banks into which the memory array is divided.Presently all DDR3 have 8 internal banks. SDRAM Chip Size 512Mb 01h1Gb 02h2Gb 03h4Gb 04hByte 5SDR

11、AM Addressing （DRAM行列地址线数目）This byte describes the row addressing and column addressing in the SDRAM Device.512Mb chips 13 Row X 10 Column 09h 13 Row X 12 Column 0Bh12 Row X 10 Column 01h1Gb chips 14 Row X 10 Column 11h14 Row X 12 Column 13h13 Row X 10 Column 09h2Gb chips 15Row X 10 Column 19h15 Row

12、 X 12 Column 1Bh14 Row X 10 Column11hByte 6 （预留）Reserved 00hByte 7 （内存module架构）Module OrganizationThis byte describes the organization of the SDRAM module; the number of Ranks and the Device Width of each DRAM(When CST EZ-SPD Programmer is used: Simply select number of Ranks and Device Width. It aut

13、omatically calculate final hex number)1 Rank module using X8 chips 01h2 Rank module using X8 chips09h1 Rank module using X4 chips00h2 Rank module using X4 chips08h4 Rank module using X8 chips 19h4 Rank module using X4chips18h1 Rank module using X16 chips02h2 Rank module using X16 chips0AhByte 8Modul

14、e Memory Bus Width （内存总位宽）This refers to the primary bus width of the module plus the additional with provided by ECC16bit01h32bit04h64bit (no parity)03h64bit + ECC (72bit) 0BhByte 9Fine timebase (FTB) Dividend / Divisor （时基）This byte defines a value in picoseconds that represents the fundamental ti

15、mebase for fine grain timing calculations. This value is used as a multiplier for formulating subsequent timing parameters. The granularity in picoseconds is derived from Dividend being divided by the Divisor.Granularity:2.5ps52h5ps55hByte 10Medium Timebase (MTB) Dividend （时间参数编码所用时基的分子）Byte 11Mediu

16、m Timebase (MTB) Divisor（时间参数编码所用时基的分母）These byte defines a value in nanoseconds that represents the fundamental timebase for medium grain timing calculations. This value is used as a multiplier for formulating subsequent timing parameters. The two byte forms the Dividend and the Divisor to determin

17、e the granularity of the medium timebase.Granularity 0.125ns Byte 10 01h Byte 11 08h 0.0625ns Byte 10 01h Byte 11 0FhByte 12Minimum SDRAM Cycle Time (tCK min) （DRAM颗粒最小时钟周期）This byte describes the minimum cycle time for the module in medium timebase (MTB) units.For MTB granularity = 0.125ns (Byte 10

18、 and Byte 11)DDR3 400Mhz clock (800data rate) 14hDDR3 533Mhz clock (1066data rate) 0FhDDR3 667Mhz clock (1333data rate) 0ChDDR3 800Mhz clock (1600data rate) 0AhByte 13 （预留）Reserved 00hByte 14CAS Latencies Supported, Low Byte （支持CL值范围，低位字节）(When CST EZ-SPD Programmer is used: Simply select all latenc

19、ies supported from table. Automatically calculate the hi and low byte hex value base on binary number)Latency 5.6 supported06hLatency 6 supported04hLatency 6,7 supported0ChLatency 5, 6, 7, 8 supported1EhByte 15 CAS Latencies Supported, High Byte 00h （支持CL值范围，高位字节）Byte 16Minimum CAS Latency Time (tAA

20、min) （CAS延迟平均时间tAAmin）Minimum CAS Latency based on medium timebase (MTB) units. tAAmin can be read off SDRAM data sheet.Based on medium timebase of 0.125nstAAmin 12.5nsDDR3-800D 64h 15nsDDR3-800E 78h11.25nsDDR3-1066E 5Ah13.125nsDDR3-1066F 69h15nsDDR3-1066G 78h10.5nsDDR3-1333F 54h12nsDDR3-1333G 60h13

21、.5ns DDR3-1333H 6Ch15ns DDR3-1333J 78h10ns DDR3-1600G 50h11.25ns DDR3-1600H 5Ah12.5 ns DDR3-1600J 64h13.75ns DDR3-1600K 6EhByte 17Minimum Write Recovery Time (tWRmin) （最小写恢复时间tWRmin）This byte defines the minimum SDRAM write recovery time in medium timebase (MTB) units. This value is read from the DD

22、R3 SDRAM data sheet.Based on medium timebase of 0.125nstWR min 15ns 78h12ns 60h16ns 80hByte 18Minimum RAS# to CAS# Delay time (tRCDmin) （RAS到CAS的延迟时间tRCDmin）This byte defines the minimum SDRAM RAS# to CAS# Delay in (MTB) unitsBased on medium timebase of 0.125nstRCD min 12.5nsDDR3-800D 64h 15nsDDR3-8

23、00E 78h11.25nsDDR3-1066E 5Ah 13.125nsDDR3-1066F 69h 15nsDDR3-1066G 78h10.5nsDDR3-1333F 54h12nsDDR3-1333G 60h15nsDDR3-1333J 78h10nsDDR3-1600G 50h11.25ns DDR3-1600H 5Ah12.5 ns DDR3-1600J 64h13.75ns DDR3-1600K 6EhByte 19Minimum Row Active to Row Active Delay time (tRRDmin) （ROW激活命令间隔时间tRRDmin）This byte

24、 defines the minimum SDRAM Row Active to Row Active Delay in (MTB) units. This can be read from the SDRAM data sheet.Based on medium timebase of 0.125nstRRD min 6.0 ns30h 7.5 ns3Ch10 ns50hByte 20Minimum Row Precharge Delay Time (tRPmin) （预充电precharge延迟时间tRPmin）This byte defines the minimum SDRAM Row

25、 Precharge Delay in (MTB) units. This can be read from the SDRAM data sheet.Based on medium timebase of 0.125nstRP min 12.5nsDDR3-800D 64h 15nsDDR3-800E 78h13.125ns DDR3-1066F 69h15nsDDR3-1066G 78h10.5nsDDR3-1333F 54h12nsDDR3-1333G 60h13.5nsDDR3-1333H 6Ch15ns DDR3-1333J 78h10ns DDR3-1600G 50h11.25ns

26、 DDR3-1600H 5Ah12.5 ns DDR3-1600J 64h13.75ns DDR3-1600K 6EhByte 21Upper Nibbles for tRAS and tRC （tRAS和tRC时间的高位字节）This byte makes up the MSB (upper 4 bits) of the tRAS (bits 3-0) and tRC (bits 7-4) for Byte 22 (tRAS lower byte) and Byte 23 (tRC lower byte). They are in (MTB) units. Based on medium t

27、imebase of 0.125nsThese nibbles represents the value of 256 (in MTB units) for both the tRAS and tRC upper nibble. Therefore, the value is always11hByte 22Minimum Active to Precharge Delay Time (tRAS min), Least Significant Byte（激活到预充电延迟时间tRAS的低位字节）This byte is the lower 8 bits of the 12 bit tRAS value. It is r