lab04.docx

1、lab04Lab 4: Looking Under the HoodTargeting XUP Spartan-3ELooking Under the HoodIntroductionIn this lab, you will gain insight into the costs of various system abstractions, such as saturation arithmetic, rounding, and additional latency. This lab makes use of the Xilinx System Generators resource E

2、stimator block to estimate the hardware resources usage in each abstractions case and View RTL Schematic viewer available in XST to view the functional design. Note: There are completed examples in c:xupdsp_flowlabslab4lab4_soln.Objectives After completing this lab, you will be able to: Understand t

3、he effect of quantization and overflow parameters Understand the implications of saturation arithmetic and rounding Use the Resource Estimator block to estimate the resource utilization View the results of your decisions in an RTL viewerDesign DescriptionThe design is a simple addsub block for which

4、 you will modify system parameters on the addsub (xladdsub) block and observe the effect on the generated hardware.Figure 4-1. System Generator addsub Design for Hardware ComparisonProcedure This lab comprises six primary steps. You will use the provided design in Simulink and estimate the resources

5、 using the Resource Estimator block in Step 1. Using the System Generator block, you will generate the design in Step 2. In Step 3, the design is implemented and the post-map report is utilized to estimate the resources. This step illustrates different ways to determine the resource utilization. Ste

6、ps 4 through 6 require you to change the overflow and quantization characteristics, implement the design, and understand the implication in hardware using the XST View RTL Schematic viewer of Xilinx ISE 6. Below each general instruction for a given procedure, you will find accompanying step-by-step

7、directions and illustrated figures providing more detail for performing the general instruction. If you feel confident about a specific instruction, feel free to skip the step-by-step directions and move on to the next general instruction in the procedure.Note: If you are unable to complete the lab

8、at this time, you can download the lab files for this module from the Xilinx University Program site at Estimate Resources Using Resource Estimator Step 1General Flow for this Lab:Step 4: Modify Overflow Step 3: Implement DesignStep 2: Generate the DesignStep 1:Estimate ResourcesStep 5: Modify Quant

9、ization Step 6: Modify Quantization and OvervlowOpen the addsub.mdl model in MATLAB and add the Resource Estimator block from Xilinx Blockset Index. Double-click the addsub block and click the Use Placement Information for Core check box. Double-click the resource Estimator block and click the Estim

10、ate Area button Open the MATLAB command window by double-clicking the MATLAB icon on your desktop, or go to Start Menu Programs MATLAB 7.0 MATLAB 7.0 Change directory to c:/xup/dsp_flow/labs/lab4/: Type cd c:/xup/dsp_flow/labs/lab4/ in the command window Open the addsub.mdl Note: The addsub.mdl desi

11、gn has truncate for the quantization and wrap for overflow Double-click the AddSub block to open the parameters block Make sure the Use core placement information check box is UncheckedFigure 4-2. The AddSub block Parameters. Double-click the Resource Estimator block Select Estimate from the drop-do

12、wn box and click the Estimate buttonFigure 16-3. Estimate Resources Using the Estimate Area Button.1. What is the resource utilization estimate? Number of Slices: Number of LUTs: Number of IOBs: Generate the Design “As Is” to get a Baseline Step 2General Flow for this Lab:Step 4: Modify Overflow Ste

13、p 3: Implement DesignStep 2: Generate the DesignStep 1:Estimate ResourcesStep 5: Modify Quantization Step 6: Modify Quantization and OvervlowUsing the System Generator block, generate the baseline design with the following settings Compilation: HDL Netlist Product Family: Spartan-3E xc3s500e-4fg320

14、Target Directory: /run1 Synthesis Tool: XST Double-click the System Generator block Browse to the current directory (c:/xup/dsp_flow/labs/lab4/) as the Target Directory Set the device related fields as listed below and click the Generate button Compilation: HDL Netlist Product Family: Spartan3e xc3s

15、500e-4fg320 Target Directory: /run1 Synthesis Tool: XSTView RTL Schematic and Estimate Resources Step 3General Flow for this Lab:Step 4: Modify Overflow Step 3: Implement DesignStep 2: Generate the DesignStep 1:Estimate ResourcesStep 5: Modify Quantization Step 6: Modify Quantization and OvervlowOpe

16、n the addsub_cw.ise project in the Xilinx ISE 8 environment. Synthesize and implement the design using the default settings. View the synthesized design using the XST View RTL Schematic viewer. Open the addsub_cw.ise project in Xilinx ISE 8 from c:xupdsp_flowlabslab4run1 Select addsub_cw.vhd in the

17、Sources in Project window Double-click View RTL Schematic under Synthesis Highlight the top-level block and click the Push button in the top menu to push down into the hierarchy to view addsub_x_0 Review the schematic and close the viewerFrom Simulink window, estimate the resources using post-map re

18、port of the implemented design Double-click the Resource Estimator block in the Simulink design window Select the Post-Map and click the Estimate button, which will run implementation in the background The resources are computed using the post-map report2. What is the post-map resource utilization e

19、stimate? Number of Slices: Number of LUTs: Modify the Overflow Characteristic Step 4General Flow for this Lab:Step 4: Modify Overflow Step 3: Implement DesignStep 2: Generate the DesignStep 1:Estimate ResourcesStep 5: Modify Quantization Step 6: Modify Quantization and OvervlowChange the addsub bloc

20、k parameters overflow properties to Saturation arithmetic. Generate the VHDL code and implement the design. View the synthesized design using the XST View RTL Schematic viewer, and determine the resources using Post-Map report. Double-click the addsub block in the System Generator model In the Outpu

21、t Type tab, select Saturate for Overflow, and then simulate Change the target directory to run2 and regenerate the design Open addsub_cw.ise in run2 and select addsub_cw.vhd in the Sources in Project window in the Xilinx ISE 8 Open down Synthesize in the Processes for Current Source and double-click

22、 View RTL Schematic Understand the schematic and close the viewer3. What do you observe in the RTL view? Use post-map report to estimate the resources4. What is the post-map resource utilization estimate? Number of Slices: Number of LUTs: Close the projectModify the Quantization Characteristic Step

23、5General Flow for this Lab:Step 4: Modify Overflow Step 3: Implement DesignStep 2: Generate the DesignStep 1:Estimate ResourcesStep 5: Modify Quantization Step 6: Modify Quantization and OvervlowChange back the addsub block parameters Overflow properties to Wrap and select the Quantization to Roundi

24、ng. Generate the VHDL code and implement the design. View the synthesized design using the XST View RTL Schematic viewer. Double-click the addsub block in the System Generator model In the Output Type tab, set Overflow to Wrap and Quantization to Round, and then simulate. Change the target directory

25、 to run3 and regenerate the design: Click Generate Open the addsub_clk_wrapper.ise project in the Xilinx ISE 8 Select addsub_clk_wrapper.vhd in the Sources in Project window Open down Synthesize in the Processes for Current Source and click the View RTL Schematic Understand the schematic and close t

26、he viewer5. What do you observe in the RTL view? Use the Resource Estimator to generate the post-map area6. What is the post-map resource utilization? Number of Slices: Close the projectModify the Quantization and Overflow Characteristics Step 6General Flow for this Lab:Step 4: Modify Overflow Step

27、3: Implement DesignStep 2: Generate the DesignStep 1:Estimate ResourcesStep 6: Modify Quantization and OvervlowStep 5: Modify Quantization Change the addsub block parameters Overflow properties to Saturation and Quantization to Rounding. Generate the VHDL code and implement the design. View the synt

28、hesized design using the XST View RTL Schematic viewer. Double-click the addsub block in the System Generator model In the Output Type tab, select Saturate for Overflow and Round for Quantization Change the target directory to run4 Regenerate the design Open the addsub_cw.ise project in the Xilinx I

29、SE 8 Select addsub_cw.vhd in the Sources in Project window Open down Synthesize in the Processes for Current Source and click View RTL Schematic Understand the schematic and close the viewer7. What do you observe in the RTL view? Determine the resource utilization with the Resource Estimator8. What

30、is the post-map resource utilization? Number of Slices: Close the project Conclusion In this lab, you learned what quantization and overflow parameters do. You were able to estimate the resource utilization using the Resource Estimator block. You also observed the implications of saturation arithmet

31、ic and rounding in the hardware. Additionally, you were familiarized with the XST View RTL Schematic Viewer.Answers 1. What is the resource utilization estimate? Number of Slices: 5 Number of LUTs: 10 Number of IOBs: 29 The RTL view of the baseline design shows that no additional hardware is required on the