1、eda考试题及答案题分为两部分!第一部分画图制pcb 版!分9个图,要分别进行练习!如下:1、用protel99画出原理图,并制出相应的3000*3000(mil)PCB板其中:U1的封装为DIP14,U2的封装为DIP16,R1、R2的封装为AXIAL0.3,C1的封装为RAD0.2,Y1的封装为XTAL1,S1的封装为DIP16,J2的封装为SIP2。2、用protel99画出原理图,并制出相应的3000*3000(mil)PCB板其中:R1、R2、R3、R4、Rc、RL的封装为AXIAL0.4,Rw的封装为VR3,C1、C2、Ce的封装为RB.2/.4,Q1的封装为TO-92A,J1、J
2、2的封装为SIP2。3、用protel99画出原理图,并制出相应的2000*2000(mil)PCB板其中:R1、R2、R3的封装为AXIAL0.4,R的封装为VR2,UA741的封装为DIP8,JP1、JP2的封装为SIP2。4、用protel99画出原理图,并制出相应的3000*3000(mil)PCB板其中:R1、R2、R3、R4、R5、R6、R7的封装为AXIAL0.4,U1、U2、DS1的封装为DIP16。5、用protel99画出原理图,并制出相应的2000*2000(mil)PCB板其中:U1、U2的封装为DIP14,J1、J2的封装为SIP2。6、用protel99画出原理图,
3、并制出相应的2000*2000(mil)PCB板其中:U1的封装为DIP16,U2、U3的封装为DIP14, J2的封装为SIP3。7、用protel99画出原理图,并制出相应的2000*3000(mil)PCB板其中:R1、R2、R3、R4、R5、R6、R7的封装为AXIAL0.4,Rw的封装为VR3,U1的封装为DIP8, J1的封装为SIP2。8、用protel99画出原理图,并制出相应的2000*2000(mil)PCB板其中: U1的封装为DIP16,U2的封装为DIP14,J1的封装为SIP6。9、用protel99画出原理图,并制出相应的2000*2000(mil)PCB板其中:
4、U1的封装为DIP14,J1的封装为SIP2,R1、RS的封装为AXIAL0.4,R2的封装为VR3,C1的封装为RAD0.2。第二部分,eda 的仿真实验!一共19种类型;如下:1、用VHDL语言编程设计四选一电路,并在MAX+PLUS上进行仿真验证。198页LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY MUX41 IS PORT( A,B : IN STD_LOGIC; X : IN STD_LOGIC_VECTOR(3 downto 0); Y : OUT STD_LOGIC);END ENTITY MUX41;ARCHITECTURE
5、ART OF MUX41 IS SIGNAL SEL : STD_LOGIC_VECTOR(1 downto 0);BEGIN SEL=B&A; PROCESS (X, SEL)IS BEGIN IF(SEL=00) THEN Y=X(0); ELSIF (SEL=01) THEN Y=X(1); ELSIF (SEL=10)THEN Y=X(2); ELSE Y=X(3); END IF; END PROCESS ; END ART;2、用VHDL语言编程设计四舍五入判别电路,输入为BCD码,输入大于等于五时,输出为1,否则为0,并在MAX+PLUS上进行仿真验证。讲过。LIBRARY IE
6、EE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SHE IS PORT( A,B,C,D : IN STD_LOGIC; y : OUT STD_LOGIC);END SHE;ARCHITECTURE A OF SHE ISBEGIN Y=D OR (C AND A)OR(C AND B); END A;3、用VHDL语言编程设计八位双向总线缓冲器,EN=0时缓冲器工作,DIR=0时,由A向B传送数据,DIR=1时,由B向A传送数据,并在MAX+PLUS上进行仿真验证。200页LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTI
7、TY BIDIR IS PORT( EN,DIR : IN STD_LOGIC; A,B : INOUT STD_LOGIC_VECTOR(7 downto 0);END BIDIR;ARCHITECTURE a OF BIDIR IS SIGNAL AOUT,BOUT: STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN PROCESS (A,EN,DIR) IS BEGIN IF (EN=0)AND(DIR=1) THEN BOUT=A; ELSE BOUT =ZZZZZZZZ; END IF; B=BOUT; END PROCESS ; PROCESS(B,EN,DI
8、R) IS BEGIN IF (EN=0AND DIR=1) THEN AOUT =B; ELSE AOUT=ZZZZZZZZ; END IF; A=AOUT; END PROCESS;END a;4、用VHDL语言编程设计带使能端的8-3线优先编码器,并在MAX+PLUS上进行仿真验证。196页LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY ENCODER1 IS PORT( A,B,C,D,E,F,G,H : IN STD_LOGIC; Y0,Y1,Y2 : OUT STD_LOGIC
9、);END ENCODER1;ARCHITECTURE ART OF ENCODER1 IS SIGNAL SY: STD_LOGIC_VECTOR(2 DOWNTO 0);BEGIN PROCESS (H,G,F,E,D,C,B,A)IS BEGIN IF H=1 THEN SY=111; ELSIF G=1 THEN SY=110; ELSIF F=1 THEN SY=101; ELSIF E=1 THEN SY=100; ELSIF D=1 THEN SY=011; ELSIF C=1 THEN SY=010; ELSIF B=1 THEN SY=001; ELSIF A=1 THEN
10、SY=000; ELSE SY=XXX; END IF; END PROCESS; Y0=SY(0); Y1=SY(1); Y2=SY(2); END ART;5、用VHDL语言编程设计带使能端的JK触发器,并在MAX+PLUS上进行仿真验证。202页LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JKCFQ IS PORT( J,K,CLK : IN STD_LOGIC; Q,QB : OUT STD_LOGIC);END JKCFQ;ARCHITECTURE ART OF JKCFQ IS SIGNAL Q_S,QB_S: STD_LOGIC
11、;BEGIN PROCESS (J,K,CLK)IS BEGIN IF (CLKEVENT AND CLK=1) THEN IF (J=1AND K=0) THEN Q_S=1;QB_S=0; ELSIF (J=0AND K=1) THEN Q_S=0;QB_S=1; ELSIF (J=1AND K=1) THEN Q_S=NOT Q_S;QB_S=NOT QB_S; END IF; END IF; Q=Q_S; QB=QB_S; END PROCESS; END ART;6、用VHDL语言编程设计一位全加器,并在MAX+PLUS上进行仿真验证192页-orLIBRARY IEEE;USE I
12、EEE.STD_LOGIC_1164.ALL;ENTITY OR2A IS PORT( A, B : IN STD_LOGIC; C : OUT STD_LOGIC);END OR2A;ARCHITECTURE a OF OR2A ISBEGIN C=A OR B;END a;-h_adderLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY H_ADDER IS PORT( A, B : IN STD_LOGIC; SO, CO : OUT STD_LOGIC);END H_ADDER;ARCHITECTURE a OF H_ADDER ISBEG
13、IN SO=(A OR B)AND(A NAND B); COS1,SO=S2); U2: H_ADDER PORT MAP (S2,CIN,S3,SUM); U3: OR2A PORT MAP (A=S1,B=S3,C=CO);END a;7、用VHDL语言编程设计一个8位的单向总线缓冲器,并在MAX+PLUS上进行仿真验证。200页LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY TRI_BUFS IS PORT( EN: IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 downto 0); DOUT : O
14、UT STD_LOGIC_VECTOR(7 downto 0);END ENTITY TRI_BUFS;ARCHITECTURE ART OF TRI_BUFS IS BEGIN PROCESS (EN, DIN) IS BEGIN IF (EN=1) THEN DOUT=DIN; ELSE DOUT=ZZZZZZZZ; END IF; END PROCESS ; END ART;7、用VHDL语言编程设计一个16位的单向总线缓冲器,并在MAX+PLUS上进行仿真验证。原理同上LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY TRI_BUFS1 I
15、S PORT( EN: IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(15 downto 0); DOUT : OUT STD_LOGIC_VECTOR(15 downto 0);END ENTITY TRI_BUFS1;ARCHITECTURE ART OF TRI_BUFS1 IS BEGIN PROCESS (EN, DIN) IS BEGIN IF (EN=1) THEN DOUT=DIN; ELSE DOUT=ZZZZZZZZZZZZZZZZ; END IF; END PROCESS ; END ART;8、用VHDL语言编程设计设计同步复位的触发器
16、,并在MAX+PLUS上进行仿真验证。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY TBTPCFQ IS PORT( CLK, CLR : IN STD_LOGIC; Q , QB : BUFFER STD_LOGIC);END TBTPCFQ;ARCHITECTURE a OF TBTPCFQ ISBEGIN PROCESS (CLK,CLR) BEGIN IF (CLK=1 AND CLKEVENT) THEN IF (CLR=1) THEN Q = 0; QB = 1; ELSE Q = NOT Q; QB = NOT QB; END I
17、F; END IF; END PROCESS ;END a;9、用VHDL语言编程设计同步复位的T触发器,并在MAX+PLUS上进行仿真验证。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY TBTCFQ IS PORT( CLK, CLR, T : IN STD_LOGIC; Q , QB : BUFFER STD_LOGIC);END TBTCFQ;ARCHITECTURE a OF TBTCFQ ISBEGIN PROCESS (CLK,CLR,T) BEGIN IF (CLK=1 AND CLKEVENT) THEN IF (CLR=1)
18、THEN Q = 0; QB = 1; ELSIF(T=0) THEN Q = Q; QB = QB; ELSE Q = NOT Q; QB = NOT QB; END IF; END IF; END PROCESS ; END a;9、用VHDL语言编程设计带使能端的T触发器,并在MAX+PLUS上进行仿真验证。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SNTCFQ IS PORT( CLK, EN, T : IN STD_LOGIC; Q , QB : BUFFER STD_LOGIC);END SNTCFQ;ARCHITECTURE
19、a OF SNTCFQ ISBEGIN PROCESS (CLK,EN,T) BEGIN IF EN=0 THEN NULL; ELSIF (CLK=1 AND CLKEVENT) THEN IF(T=0) THEN Q = Q; QB = QB; ELSE Q = NOT Q; QB = NOT QB; END IF; END IF; END PROCESS ; END a;10、用VHDL语言编程设计8位寄存器,并在MAX+PLUS上进行仿真验证。203页LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY REG IS PORT( CLK : I
20、N STD_LOGIC; D : IN STD_LOGIC_VECTOR(8 downto 0); Q : OUT STD_LOGIC_VECTOR(8 downto 0);END ENTITY REG;ARCHITECTURE ART OF REG IS BEGIN PROCESS (CLK, D) IS BEGIN IF (CLKEVENT AND CLK=1) THEN Q=D; END IF; END PROCESS ; END ART;11、用VHDL语言编程设计一个8位的移位寄存器,具有左移一位或右移一位、并行输入和同步复位的功能,并在MAX+PLUS上进行仿真验证。204页LIB
21、RARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SFTREG1 IS PORT( CLK ,RESET : IN STD_LOGIC; LSFT,RSFT : IN STD_LOGIC; DATA : IN STD_LOGIC_VECTOR(7 downto 0); MODE : IN STD_LOGIC_VECTOR(1 downto 0); QOUT : BUFFER STD_LOGIC_VECTOR(7 downto 0);END ENTITY SFTREG1;ARCHITECTURE ART OF SFTREG1 IS BEGIN PROCES
22、S IS BEGIN WAIT UNTIL(RISING_EDGE(CLK); IF (RESET=1) THEN QOUT QOUT QOUT QOUT NULL;END CASE; END IF; END PROCESS; END ARCHITECTURE ART;12、用VHDL语言编程设计带使能端的RS触发器,并在MAX+PLUS上进行仿真验证。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SNRSCFQ IS PORT( CLK, R, S, EN : IN STD_LOGIC; Q , QB : BUFFER STD_LOGIC);
23、END SNRSCFQ;ARCHITECTURE a OF SNRSCFQ ISBEGIN PROCESS (CLK,R,S,EN) BEGIN IF(EN=0) THEN NULL; ELSIF (CLK=1 AND CLKEVENT) THEN IF (S=0 AND R=0) THEN Q = Q; QB = QB; ELSIF(S=0 AND R=1) THEN Q = 0; QB = 1; ELSIF(S=1 AND R=0) THEN Q = 1; QB = 0; ELSE NULL; END IF; END IF; END PROCESS ; END a;13、用VHDL语言编程
24、设计带使能端、同步复位的RS触发器,并在MAX+PLUS上进行仿真验证。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SNTFRSCFQ IS PORT( CLK, R, S, EN, RES : IN STD_LOGIC; Q , QB : BUFFER STD_LOGIC);END SNTFRSCFQ;ARCHITECTURE a OF SNTFRSCFQ ISBEGIN PROCESS (CLK,R,S,EN,RES) BEGIN IF(EN=0) THEN NULL; ELSIF (CLK=1 AND CLKEVENT) THEN IF
25、(RES=1)THEN Q =0; QB =1; ELSIF (S=0 AND R=0) THEN Q = Q; QB = QB; ELSIF(S=0 AND R=1) THEN Q = 0; QB = 1; ELSIF(S=1 AND R=0) THEN Q = 1; QB = 0; ELSE NULL; END IF; END IF; END PROCESS ; END a;14、用VHDL语言编程设计异步复位的D触发器,并在MAX+PLUS上进行仿真验证。201页LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ASYNDCFQ IS POR
26、T( D,CLK,PRESET,CLR : IN STD_LOGIC; Q : OUT STD_LOGIC );END ENTITY ASYNDCFQ;ARCHITECTURE ART OF ASYNDCFQ IS BEGIN PROCESS(CLK,PRESET,CLR)IS BEGIN IF (PRESET=1) THEN Q=1; ELSIF (CLR=1) THEN Q=0; ELSIF (CLKEVENT AND CLK=1)THEN Q=D; END IF; END PROCESS; END ARCHITECTURE ART;15、用VHDL语言编程设计带同步复位功能的D触发器,并在MAX+PLUS上进行仿真验证。202页LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SYNDCFQ1 IS PORT( D,CLK,RESET : IN STD_LOGIC; Q : OUT STD_LOGIC );END ENTITY SYNDCFQ1;ARCHITECTURE ART OF SYNDCFQ1 IS BEGIN
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