M12153DHA.docx

1、M12153DHA Monitor Development Display & Development Division IMES Co., Ltd.TFT Color LCD Module M121-53DHA Product Specifications30.8cm(12.1inch) SVGA(800x600)JUL 31, 2001Rev. & dateContent of changeRev.1.0SEP 04, 2000Initial ReleaseRev.2.0APR 27, 2001PDF fileRev.3.0JUL 31, 2001EC correction Prepare

2、d by E. Hiratsuka Approved by M.Ozawa ScopeM121-53DH is a TFT LCD color module to be designed to realize the largest screen on A4 size notebook style personal computer, PC monitor and industry application. In addition to its large screen, the characteristics of this module are high luminance, light

3、weight, slim/thin outline, low power consumption and high resolution of SVGA (800x600) capability. Features Application . 30.8cm(12.1 inch) diagonal . Notebook PCs . Native 262k colors (R/G/B 6 bit each) . Monitors . SVGA 800 x 600 pixels . Low Reflection (Black Matrix) . Two lamps backlight . 250 c

4、d/m2 high luminance . 278mm x 205mm x 12mm typ. (Need min. 3mm clearance from lamp cables) . 465 g typ. . 7.85 W typ. Notes . The construction of M121-53DH is to add a TTL RGB to LVDS conversion card (SN75LVDS84A) to M121-53DR (LVDS input) TFT LCD Module. Therefore, the input of M121-53DH is compati

5、ble to M121-53HR.This module does not contain an inverter card for backlight.The LCD cell is supplied from IBM.1. Characteristics SummaryScreen Diagonal30.8cm (12.1)Active Area246.0mm(H) x 184.5mm(V)Pixel Format800(x3) x 600Pixel Pitch0.3075(per one triad) x 0.3075Pixel ArrangementR,G,B Vertical Str

6、ipeDisplay ModeNormally WhiteWhite Luminance250 cd/m2 typ.(CFL Discharge Current = 5.0 mArms x2)Contrast Ratio150 : 1 typ.Viewing Angle DegreesHorizontal (Right) 40 minK=10 (Left) 40 minK:Contrast RatioVertical (Upper) 10 minK=10 (Lower) 20 minOptical Rise Time/Fall Time30 msec typ.Nominal Input Vol

7、tage VDD+3.3 VPower Consumption (w/o inverter)(VDD line + two lamps input line)7.85 W typ.Weight465 grams typ.Physical Size278mm x 205mm x 12mm typ.(Need min 3mm clearance from lamp cables.Electrical InterfaceDigital Video Signals(6-bit for each Corlor G/B)Sync. Signal (x4)Supported colorsNative 262

8、k colorsScreen CriteriaDOT defect: LIT : 6 UNLIT : - Total DOT Defect : 15 Double LIT : 2 Double UNLIT : - Distance LIT : 3 , 20mmLine Defect: No line DefectBacklight lamp life (Luminance becomes half value of initial value.)30,000 Hours under following condition. - Temp = 25 degC - Continues power

9、onTemperature RangeOperatingStorage+0 to +50 degC-20 to +60 degC2. Absolute Maximum Ratings Electrical Absolute Maximum RatingsRatingSymbolValueUnitConditionsSupply VoltageVDD-0.3 to +4.0VLamp ignition ltageVcfl1500VrmsAt 0 degreeCCFL Discharge CrrentIcfl5.5mArmsExclude inrush currentCFL Inrush Curr

10、entIrcfl30mA0-pWith Max. duration = 50 (mSec)CFL Driving equencyfcfl30 to 70kHzAt 25 degreeCStatic ElectricityOperators should be grounded in handling the TFT LCD Module Environmental Absolute Maximum RatingsRatingSymbolValueUnitConditionsStorage TemperatureTST-20 to +60degCAt the glass surfaceOpera

11、tion TemperatureTOP0 to +50degCAt the glass surfaceOperation Humidity8 to 95%RHMax wet bulb temp. 29 degCNo condensationVibration1.5G10-200Hz,X,Y,Z (Note1)Trapezoidal Shock50G18msec, +/-X,Y,Z (Note1)Corrosive GasNot Acceptable Note 1: At testing Vibration and Shock, the fixture in holding the Module

12、 to be tested have to be hard rigid enough so that the Module would not be twisted or bent by the fixture.3. Color Arrangement800THTRIAD. . . . . . . . . . . . . . . . . . . .R G BR G BR G BR G BR G BR G B1STLINE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13、. . . . . . . . . . . . . . . . . . . . . . . . . . . .R G BR G BR G BR G B. . . . . . . . . . . . . . . . . . . .600THLINE4. Block Diagram LCD-DRIVE Connector (41pin) Y-Driver Backlight Unit TFT ARRAY / CELL 800 (R/G/B) x 600LCD DRIVE CARD 6 bit color data for R/G/BLCDController DTCLK DSPTMGDC-DCCo

14、nverter Hsync Vsync VDD X-Driver GND Lamp Connector (3pin)5. Signal Interface 5.1 ConnectorsPhysical interface is described as for the connector on module.These connectors are capable of accommodating the following signals and will be following components.Supplier NameSuppliers Part NumberLCD Drive

15、ConnectorHIROSEDF9B-41P-1VMating ConnectorHIROSEDF9B-41S-1VSupplier NameSuppliers Part numberLamp ConnectorJSTBHR-04VS-1SBH-001T-P0.5Mating connectorJSTSM04(4.0)B-BHS-1-TB 5.2 Signal for LCD Drive ConnectorPin#Signal NamePin#Signal name1GND2-DTCLK3GND4HSYNC5VSYNC6GND7GND8GND9+RED010+RED111+RED212GND

16、13+RED314+RED415+RED516GND17GND18GND19+GREEN020+GREEN121+GREEN222GND23+GREEN324+GREEN425+GREEN526GND27GND28GND29+BLUE030+BLUE131+BLUE232GND33+BLUE334+BLUE435+BLUE536GND37+DSPTMG38Reserved39VDD (+3.3V)40VDD (+3.3V)41Reserved Note 1: Reserved pins are not allowed to connect any other line. Note 2: Vol

17、tage levels of all input signals are CMOS compatible (except VDD). This module shall contain column are row drivers to address any given pixel. The host attached PC system shall supply 18 bits (6bits per each color) data and 4-sync signals to these drivers and power supply for backlight. These inter

18、face signals and their timing relationship are described below.Pin No.Signal NameDescription1514131110 9+RED5+RED4+RED3+RED2+RED1+RED0Red Data 5 (MSB)Red Data 4Red Data 3Red Data 2Red Data 1Red Data 0 (LSB)Red-Pixel-Data: Each red pixels brightness data consists of these 6 bits pixel data.2524232120

19、19+GREEN5+GREEN4+GREEN3+GREEN2+GREEN1+GREEN0Green Data 5 (MSB)Green Data 4Green Data 3Green Data 2Green Data 1Green Data 0 (LSB)Green-Pixel-Data: Each Green pixels brightness data consists of these 6 bits pixel data.353433313029+BLUE5+BLUE4+BLUE3+BLUE2+BLUE1+BLUE0Blue Data 5 (MSB)Blue Data 4Blue Dat

20、a 3Blue Data 2Blue Data 1Blue Data 0 (LSB)Blue-Pixel-Data: Each Blue pixels brightness data consists of these 6 bits pixel data.2-DTCLKData Clock: The typical frequency is 40.00MHz. The signal is used to strobe the pixel data and +DSPTMG signals. All pixel data shall be valid at the falling edge whe

21、n the +DSPTMG signal is high.37+DSPTMGDisplay Timing: This signal strobed at falling edge of DTCLK. When the signal is high, the pixel data shall be valid to be displayed.5VSYNCVertical Sync: The signal is synchronized to DTCLK.4HSYNCHorizontal Sync: The signal is synchronized to DTCLK.39,40VDD+3.3V

22、1,3,6,7,8,12,16,17,18,22,26,27,28,32,36GNDSignal Ground38,41Reserved: No connection (Signal reserved) Note: Output signals from system shall be low or Hi-Z state when VDD is off.5.3 Signal Specification Voltage levels of all input signals are CMOS compatible (except VDD). Each signal characteristics

23、 are as follows;ParameterConditionMin.Max.UnitVihHigh level input voltage R/G/B, DTCLK DSPTMG, H/V SYNC0.7xVDDVDDVVilLow level input voltage R/G/B, DTCLK DSPTMG, H/V SYNC00.2xVDDVIihHigh level input current R/G/B, DTCLK DSPTMG, H/V SYNC-50uAIilLow level input current R/G/B, DTCLK DSPTMG, H/V SYNC-50

24、uA5.4 Signal for Lamp ConnectorPin No.Signal NameDescription1 Lamp high 1 For Lamp 12 Lamp High 2 For Lamp 24 Lamp Low For Lamp 1&26. Lamp Interface Specification and Guide Line for CFL Inverter Parameter NameSymbol Min.Typ. Max.Unit NoteCFL Kick-off Voltage Vs - -1,100VrmsTamb=25degC*4 - -1,500Tamb

25、=0degC*4CFL Discharge Current(per one lamp) Icfl1.5*6 - 5.5mArmsTotal operating range -5.0 -Screen 250cd/m2,at Tamb=25degCCFL Discharge Voltage Vcfl -650 -VrmsScreen 250cd/m2,at Tamb=25degCCFL Power Consumption Pcfl -6.5 - WScreen 250cd/m2,at Tamb=25degCCFL Discharge Frequency Fcfl 30 40 70*6 kHzRef

26、erence*5Note*1 All of characteristics listed are measured under the condition using the IMES inverter(IMES P/N 6M000704).*2 In case of using an inverter other than listed, it is recommended to check the inverter carefully. Sometimes, interfering noise stripes appear on the screen, and substandard lu

27、minance or flicker at low power may happen.*3 In designing an inverter, it is suggested to check safety circuit very carefully. Impedance of CFL, for instance, becomes more than 1 M ohm when CFL is damaged.*4 Generally, CFL has some amount of delay time after applying kick-off voltage. It is recomme

28、nded to keep on applying kick-off voltage for 1 Sec until discharge.*5 CFL discharge frequency must be carefully chosen so as not to produce interfering noise stripes on the screen.*6 Reducing CFL current increases CFL discharge voltage and generally increases CFL discharge frequency. So all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high-voltage output of the inverter. 7. Interface TimingsBasically, interface