eda编程.docx

1、eda编程十六位加法器实验编程和仿真结果LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADDER IS PORT(A,B:IN STD_LOGIC_VECTOR(15 DOWNTO 0); SUM:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);END ADDER;ARCHITECTURE behav OF ADDER ISBEGIN SUM=A+B;END behav;四位的二选一多路选择器编程及仿真结果LIBRARY IEEE;USE IEEE.STD_LO

2、GIC_1164.ALL;ENTITY MUX4 IS PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0 ); SEL :INTEGER RANGE 0 TO 1 ; Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END MUX4;ARCHITECTURE behav OF MUX4 IS BEGIN PROCESS(SEL) BEGIN IF SEL=0 THEN Y=A; ELSE YA=1;B=1;C=1;D=1;E=1;F=1;GA=0;B=1;C=1;D=0;E=0;F=0;GA=1;B=1;C=0;D=1;E=1;F=0;GA=

3、1;B=0;C=0;D=1;E=1;F=1;GA=1;B=0;C=1;D=0;E=0;F=1;G=1;END CASE;END PROCESS;END behav;8位16位移位器编程及仿真结果LIBRARY IEEE;USE IEEE.std_logic_1164.all;USE IEEE.std_logic_arith.all;USE IEEE.std_logic_unsigned.all;ENTITY shifter ISPORT ( input : IN std_logic_vector(7 downto 0); cnt : IN std_logic_vector(1 downto 0

4、); result : OUT std_logic_vector(15 downto 0) );END shifter;ARCHITECTURE logic OF shifter ISBEGINPROCESS(input, cnt)VARIABLE temp : std_logic_vector(15 downto 0); BEGIN temp(15 downto 8) := 00000000; temp(7 downto 0) := input; IF cnt = 01 THEN FOR i IN 15 DOWNTO 4 LOOP temp(i) := temp(i-4); END LOOP

5、; temp(3 downto 0) := 0000; ELSIF cnt = 10 THEN FOR i iN 15 DOWNTO 8 LOOP temp(i) := temp(i-8); END LOOP; temp(7 downto 0) := 00000000; ELSE temp := temp; END IF; result = temp; END PROCESS;END logic;A 16位同步寄存器编程及仿真结果LIBRARY IEEE;USE IEEE.std_logic_1164.all;USE IEEE.std_logic_unsigned.all;ENTITY reg

6、 ISPORT ( CLK, CLKEN, CLR : IN std_logic; IN_REG : IN std_logic_vector(15 downto 0); OUT_REG : OUT std_logic_vector(15 downto 0);END reg;ARCHITECTURE logic OF REGISBEGINPROCESS(clk)BEGIN IF rising_edge(clk) THEN IF clken = 0 THEN IF clr = 1 THEN OUT_REG = in_reg; ELSIF clr = 0 THEN OUT_REG 0); END I

7、F; END IF; END IF; END PROCESS;END logic;B 2位异步计数器编程及仿真结果LIBRARY IEEE;USE IEEE.std_logic_1164.all;USE IEEE.std_logic_unsigned.all;ENTITY counter ISPORT ( clk, clr : IN std_logic; sum : OUT std_logic_vector(1 downto 0);END counter;ARCHITECTURE logic OF counter ISBEGINPROCESS(clk,clr)VARIABLE count :

8、std_logic_vector(1 downto 0); BEGIN IF clr = 0 THEN count := 00; sum = count; ELSIF rising_edge(clk) THEN count := count + 1; sum = count; END IF;END PROCESS;END logic;A 状态机的编程及仿真结果LIBRARY IEEE;USE IEEE.std_logic_1164.all;USE IEEE.std_logic_unsigned.all;ENTITY control ISPORT ( clk, rst, start : IN s

9、td_logic; count : IN std_logic_vector(1 downto 0); in_sel, shift : OUT std_logic_vector(1 downto 0); state_out : OUT std_logic_vector(2 downto 0); done, clken, regclr : OUT std_logic );END control;ARCHITECTURE logic OF control ISTYPE state_type IS (idle, lsb, mid, msb, err);SIGNAL code : state_type;

10、 BEGIN PROCESS (rst, clk) BEGIN IF rst = 1 THEN code IF start = 1 THEN code = lsb; ELSE code IF start = 0 and count = 00 THEN code = mid; ELSE code IF start = 0 and count = 10 THEN code = msb; ELSIF start = 0 and count = 01 THEN code = mid; ELSE code IF start = 0 and count = 11 THEN code = idle; ELS

11、E code IF start = 1 THEN code = lsb; ELSE code code IF start = 1 THEN in_sel = XX; shift = XX; done = 0; clken = 1; regclr = 0; ELSE in_sel = XX; shift = XX; done = 0; clken = 1; regclr IF start = 0 and count = 00 THEN in_sel = 00; shift = 00; done = 0; clken = 0; regclr = 1; ELSE in_sel = XX; shift

12、 = XX; done = 0; clken = 1; regclr IF start = 0 and count = 10 THEN in_sel = 10; shift = 01; done = 0; clken = 0; regclr = 1; ELSIF start = 0 and count = 01 THEN in_sel = 01; shift = 01; done = 0; clken = 0; regclr = 1; ELSE in_sel = XX; shift = XX; done = 0; clken = 1; regclr IF start = 0 and count

13、 = 11 THEN in_sel = 11; shift = 10; done = 1; clken = 0; regclr = 1; ELSE in_sel = XX; shift = XX; done = 0; clken = 1; regclr IF start = 1 THEN in_sel = XX; shift = XX; done = 0; clken = 1; regclr = 0; ELSE in_sel = XX; shift = XX; done = 0; clken = 1; regclr IF start = 1 THEN in_sel = XX; shift =

14、XX; done = 0; clken = 1; regclr = 0; ELSE in_sel = XX; shift = XX; done = 0; clken = 1; regclr state_out state_out state_out state_out state_out state_out = 000; END CASE; END PROCESS moore;END logic;B 4x4乘法器的编程及仿真结果LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY lpm;USE lpm.lpm_components.all;ENTI

15、TY mult4x4 IS PORT ( dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );END mult4x4;ARCHITECTURE SYN OF mult4x4 ISSIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);COMPONENT lpm_mult GENERIC ( lpm_hint : STRING; lpm_represe

16、ntation : STRING; lpm_type : STRING; lpm_widtha : NATURAL; lpm_widthb : NATURAL; lpm_widthp : NATURAL; lpm_widths : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT;BEGIN result MAXIMIZE_SPEED=5, lpm_representation = UNSIGNED, lpm_type = LPM_MULT, lpm_widtha = 4, lpm_widthb = 4, lpm_widthp = 8, lpm_widths = 1 ) PORT MAP ( dataa = dataa, datab = datab, result = sub_wire0 )END SYN;C 88乘法器的顶层电路的实现