高速模拟Turbo译码英汉双语.docx

1、高速模拟Turbo译码英汉双语郑州轻工业学院本科毕业设计（论文）英文翻译题 目 高速模拟Turbo译码 学生姓名 专业班级 学 号 院 （系） 计算机与通信工程学院 指导教师(职称) 完成时间 2012年4月10日 英文原文A High-Speed Analog Turbo DecoderFotios Gioulekas, Michael Birbas, Alex Birbas, and George Bilionis, Non-membersABSTRACT：A new type of iterative decoders based on analog computing networks

2、, which are used to decode powerful error-correcting schemes, such as Turbo and Low-density parity-check (LDPC) codes, outperform their digital counterparts in terms of power consumption and speed. Only few analog Turbo decoders, all of them based on CMOS subthreshold technology have been implemente

3、d till now. This paper aims to present the design and enhanced functionality of an all-analog Turbo decoder taking advantage of high-speed features of SiGe HBTs achieving throughput up to Gbits/s. Simulation results based on AMS 0.35m SiGe BiCMOS technology demonstrate promising performance compared

4、 to existing designs.Keywords: Analog Turbo Decoder, High speed,SiGe benefits.1. INTRODUCTIONThe superior performance of Turbo 1 and LDPC 2 codes, which almost “touch” the theoretical Shannon capacity limit offer great channel coding gains in telecommunication systems providing low bit and frame err

5、or rates at significant low signal to noise ratios. Researchers 3, 4, 5 have observed that this important class of algorithms can be efficiently represented using graphical models (factor graphs).These error-correcting schemes are based on iteratively passing messages (soft information), which corre

6、spond to probability mass functions, and their execution can be interpreted as an instance of a general“sum-product algorithm (SPA) 5”. It has been shown 3 that this algorithm is identical to the a posteriori probability (APP)-BCJR algorithm 6 used in Turbo decoding. The main advantages of this grap

7、hical representation are the easy visualization of the algorithm and the simplification of the corresponding equations leading to low-power execution graphs. Digital implementations of Turbo codes and their representative SPA algorithm require complex floating- point computations, large look up tabl

8、es and memory storage while the iterative nature of the decoding process causes long latencies, thus limiting 04PSI04: Manuscript received on December 20, 2004 ; revised on August 8, 2005. The authors are with the Department of Electrical and Computer Engineering University of Patras Campus of Rion,

9、 26500, Greece. E-mail:fgiou, mbirbas, birbas, bilionis ee.upatras.gr significantly the decoding speed and increasing the power consumption. However, the direct mapping of the SPA algorithm into analog translinear circuits that has been proposed lately outperforms comparable digital decoders improvi

10、ng the ratio of speed to power consumption by two orders of magnitude 7. Furthermore, a digital error-correcting decoder has to estimate the original message by processing the received analog signal, a task that requires A/D converters of significant resolution. This denotes that the availability of

11、 an analog decoder would give the ability to directly process the incoming signal in its natural form avoiding the A/D converter overhead. The aim of this work is to utilize directly the analog received waveform through the design of a 16-bit analog Turbo decoder in 0.35m SiGe BiCMOS technology and

12、to investigate/compare its capabilities against other existing approaches (both digital and analog). This is one of the first implementations in literature since almost all other known ones, which are few anyway, are in CMOS. The rest of the paper is organized as follows: Section 2 reports the relat

13、ed and previous work in the field of analog decoding. In Section 3 an overview of the Turbo code scheme is given and the employed design technique is described.The decoder architecture and its performance based on simulation results are given in section 4. Finally, section 5 compares our decoder to

14、other analog and digital implementation.2. RELATED WORK AND MOTIVATIONThe concept of an all-analog decoding scheme was introduced in 1998 8 while prior work in analog implementations of Viterbi decoders 9, 10 demonstrated better performance in power consumption and speed than their corresponding dig

15、ital realizations. Implementations of small analog decoders in CMOS and conventional BiCMOS technologies of Hamming 11, tailbiting convolutional 12, 13, Turbo 14, 15,16 and LDPC 17, 18 codes have been reported as a proof-of-concept. Those analog decoders are constructed by interconnecting highly par

16、allel translinear 7 circuits. These translinear circuits work with soft (continuous) values in continuous-time and are based on the Gillbert multiplier cell 19. Some research groups 7 follow the current mode approach, where the soft-inputs and soft-outputs (SISO) 20 of the APP algorithm have the for

17、m of currents corresponding to discrete probability distributions while other research group 8, 12 follow the voltage mode approach, where log-likelihood ratios 78 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.3, NO.2 AUGUST 2005(LLRs) are represented as differential volt

18、ages. Both approaches exploit the exponential voltage-current characteristic of bipolar transistors as well as of CMOS ones when these operate in the subthreshold region. Thus, the non-linearity of the transistor is exploited rather than fought. Our work adopts the current mode approach based on the

19、 fact that the voltage mode approach is more sensitive in temperature 21. So far, really few analog implementations of Turbo decoders can be found in the literature 14, 15, 16 and almost all of them in CMOS technology. This is mainly due to the fact that CMOS transistors consume less power, but on t

20、he other hand are slower and sensitive to noise and process variations when working in the subthreshold region 22, an operation mode that is anyway difficult to maintain/control but it is necessary to keep so as to avoid losing accuracy. These are some of the reasons that led us to choose SiGe BiCMO

21、S technology and in the same time we were able to directly benefit from the superior speed of SiGe heterojunction transistors. Regarding existing implementation of Turbo decoders in SiGe, to our knowledge only one has been reported 23 indicating speed gains but they followed a different architectura

22、l approach from our case. Specifically,they used as many component APP decoders as the estimated number of the iterations to build the analog decoder (no sample-and-hold-circuits where used to feed the decoder with the voltage waveform). However,their design did not work properly and so it was not p

23、ossible to compare our design to theirs. In this work the objective is to prove the concept of realizing efficient analog implementations of Turbo decoders in SiGe technology, and to investigate/evaluate the pros and cons of such realizations while keeping the design procedure and the Turbo decoder

24、in quite realistic standards.3. DESIGN METHODOLOGY3.1 Turbo Code StructureThe Turbo encoder is constructed by the parallel concatenation of two or more recursive systematic convolutional codes (RSC), termed constituent codes. The input of the first encoder is not permuted.The input to the other enco

25、ders is permuted so that the other constituent encoders are fed with the interleaved and uncorrelated form of the information sequence.Our design refers to the turbo encoder that comprises two identical RSC codes and one cyclicshift interleaver 24. The RSC codes used are described by the following g

26、enerator polynomial:The encoding process of an RSC code can be representedby a trellis diagram, which is defined by the relevant generator polynomial. The Turbo encoderFig.1: (I) Turbo encoder structure, (II) One trellis section, (III) the turbo decoder scheme. accepts a bit information sequence u a

27、nd provides a set of outputs c = u, p, q, where p and q are the parity bits produced by RSC1 and RSC2, respectively.After the serialization of the encoder outputs,the modulator forms and transmits them through the channel. In our case the BPSK modulation scheme and the AWGN memoryless channel model

28、have been employed. Both trellises are considered truncated at the end.The Turbo decoder incorporates a parallel-to-serial (P2S) interface, which accepts the corrupted (by noise) signals and feeds them to the two APP decoders.The two decoders exchange iteratively extrinsic information. The extrinsic

29、 information, which is a reliability measure of each component decoders estimate concerning the transmitted information symbols,is based on the corresponding parity sequence only. This negative feedback scheme is responsible for the Turbo decoders stability and superior performance.After a specified

30、 number of iterations the decoder makes final hard-decisions about the transmitted information sequence.Figure 1 illustrates the Turbo encoder with 1/3rate, the trellis diagram of the constituent codes andthe Turbo decoder architecture.3.2 Factor Graph RepresentationThe Turbo encoding and decoding p

31、rocedures can be efficiently represented through a bipartite graphical model, the factor graph, which expresses how a global function of several variables is factored into a product of local functions 3. A factor graph has a variable node x for each variable, a factor node f for each local function

32、and an edge connecting a variable node x to a factor node f if and only if x is an argument of f. The final cost function-inference (a-posteriori probabilities) is computed by performing the sum-product algorithm and the node-update rules 5. Figure 2 delineates the factor graph for our Turbo coding scheme. The variable nodes Yu, Yp, Yq are represented by circles and describe the channel observations provided e.g. by the matched filter of a typical BPSK demodulator. The variable nodes U, Q, P represent the transmitted information (u) and