高速模拟Turbo译码英汉双语.docx

高速模拟Turbo译码英汉双语.docx

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高速模拟Turbo译码英汉双语

郑州轻工业学院

本科毕业设计（论文）

英文翻译

题目高速模拟Turbo译码

学生姓名

专业班级

学号

院（系）计算机与通信工程学院

指导教师（职称）

完成时间2012年4月10日

英文原文

AHigh-SpeedAnalogTurboDecoder

FotiosGioulekas,MichaelBirbas,AlexBirbas,

andGeorgeBilionis,Non-members

ABSTRACT：

Anewtypeofiterativedecodersbasedonanalogcomputingnetworks,whichareusedtodecodepowerfulerror-correctingschemes,suchasTurboandLow-densityparity-check（LDPC）codes,outperformtheirdigitalcounterpartsintermsofpowerconsumptionandspeed.OnlyfewanalogTurbodecoders,allofthembasedonCMOSsubthresholdtechnologyhavebeenimplementedtillnow.Thispaperaimstopresentthedesignandenhancedfunctionalityofanall-analogTurbodecodertakingadvantageofhigh-speedfeaturesofSiGeHBTsachievingthroughputuptoGbits/s.SimulationresultsbasedonAMS0.35μmSiGeBiCMOStechnologydemonstratepromisingperformancecomparedtoexistingdesigns.

Keywords:

AnalogTurboDecoder,Highspeed,SiGebenefits.

1.INTRODUCTION

ThesuperiorperformanceofTurbo[1]andLDPC[2]codes,whichalmost“touch”thetheoreticalShannoncapacitylimitoffergreatchannelcodinggainsintelecommunicationsystemsprovidinglowbitandframeerrorratesatsignificantlowsignaltonoiseratios.Researchers[3,4,5]haveobservedthatthisimportantclassofalgorithmscanbeefficientlyrepresentedusinggraphicalmodels（factorgraphs）.Theseerror-correctingschemesarebasedoniterativelypassingmessages（softinformation）,whichcorrespondtoprobabilitymassfunctions,andtheirexecutioncanbeinterpretedasaninstanceofageneral

“sum-productalgorithm（SPA）[5]”.Ithasbeenshown[3]thatthisalgorithmisidenticaltotheaposterioriprobability（APP）-BCJRalgorithm[6]usedinTurbodecoding.Themainadvantagesofthisgraphicalrepresentationaretheeasyvisualizationofthealgorithmandthesimplificationofthecorrespondingequationsleadingtolow-powerexecutiongraphs.DigitalimplementationsofTurbocodesandtheirrepresentativeSPAalgorithmrequirecomplexfloating-pointcomputations,largelookuptablesandmemorystoragewhiletheiterativenatureofthedecodingprocesscauseslonglatencies,thuslimiting04PSI04:

ManuscriptreceivedonDecember20,2004;revisedonAugust8,2005.TheauthorsarewiththeDepartmentofElectricalandComputerEngineeringUniversityofPatrasCampusofRion,26500,Greece.E-mail:

{fgiou,mbirbas,birbas,bilionis}@ee.upatras.grsignificantlythedecodingspeedandincreasingthepowerconsumption.However,thedirectmappingoftheSPAalgorithmintoanalogtranslinearcircuitsthathasbeenproposedlatelyoutperformscomparabledigitaldecodersimprovingtheratioofspeedtopowerconsumptionbytwoordersofmagnitude[7].Furthermore,adigitalerror-correctingdecoderhastoestimatetheoriginalmessagebyprocessingthereceivedanalogsignal,ataskthatrequiresA/Dconvertersofsignificantresolution.ThisdenotesthattheavailabilityofananalogdecoderwouldgivetheabilitytodirectlyprocesstheincomingsignalinitsnaturalformavoidingtheA/Dconverteroverhead.Theaimofthisworkistoutilizedirectlytheanalogreceivedwaveformthroughthedesignofa16-bitanalogTurbodecoderin0.35μmSiGeBiCMOStechnologyandtoinvestigate/compareitscapabilitiesagainstotherexistingapproaches（bothdigitalandanalog）.Thisisoneofthefirstimplementationsinliteraturesincealmostallotherknownones,whicharefewanyway,areinCMOS.Therestofthepaperisorganizedasfollows:

Section2reportstherelatedandpreviousworkinthefieldofanalogdecoding.InSection3anoverviewoftheTurbocodeschemeisgivenandtheemployeddesigntechniqueisdescribed.Thedecoderarchitectureanditsperformancebasedonsimulationresultsaregiveninsection4.Finally,section5comparesourdecodertootheranaloganddigitalimplementation.

2.RELATEDWORKANDMOTIVATION

Theconceptofanall-analogdecodingschemewasintroducedin1998[8]whilepriorworkinanalogimplementationsofViterbidecoders[9,10]demonstratedbetterperformanceinpowerconsumptionandspeedthantheircorrespondingdigitalrealizations.ImplementationsofsmallanalogdecodersinCMOSandconventionalBiCMOStechnologiesofHamming[11],tailbitingconvolutional[12,13],Turbo[14,15,16]andLDPC[17,18]codeshavebeenreportedasaproof-of-concept.Thoseanalogdecodersareconstructedbyinterconnectinghighlyparalleltranslinear[7]circuits.Thesetranslinearcircuitsworkwithsoft（continuous）valuesincontinuous-timeandarebasedontheGillbertmultipliercell[19].Someresearchgroups[7]followthecurrentmodeapproach,wherethesoft-inputsandsoft-outputs（SISO）[20]oftheAPPalgorithmhavetheformofcurrentscorrespondingtodiscreteprobabilitydistributionswhileotherresearchgroup[8,12]followthevoltagemodeapproach,wherelog-likelihoodratios78ECTITRANSACTIONSONELECTRICALENG.,ELECTRONICS,ANDCOMMUNICATIONSVOL.3,NO.2AUGUST2005（LLRs）arerepresentedasdifferentialvoltages.Bothapproachesexploittheexponentialvoltage-currentcharacteristicofbipolartransistorsaswellasofCMOSoneswhentheseoperateinthesubthresholdregion.Thus,thenon-linearityofthetransistorisexploitedratherthanfought.Ourworkadoptsthecurrentmodeapproachbasedonthefactthatthevoltagemodeapproachismoresensitiveintemperature[21].Sofar,reallyfewanalogimplementationsofTurbodecoderscanbefoundintheliterature[14,15,16]andalmostalloftheminCMOStechnology.ThisismainlyduetothefactthatCMOStransistorsconsumelesspower,butontheotherhandareslowerandsensitivetonoiseandprocessvariationswhenworkinginthesubthresholdregion[22],anoperationmodethatisanywaydifficulttomaintain/controlbutitisnecessarytokeepsoastoavoidlosingaccuracy.ThesearesomeofthereasonsthatledustochooseSiGeBiCMOStechnologyandinthesametimewewereabletodirectlybenefitfromthesuperiorspeedofSiGeheterojunctiontransistors.RegardingexistingimplementationofTurbodecodersinSiGe,toourknowledgeonlyonehasbeenreported[23]indicatingspeedgainsbuttheyfollowedadifferentarchitecturalapproachfromourcase.Specifically,theyusedasmanycomponentAPPdecodersastheestimatednumberoftheiterationstobuildtheanalogdecoder（nosample-and-hold-circuitswhereusedtofeedthedecoderwiththevoltagewaveform）.However,theirdesigndidnotworkproperlyandsoitwasnotpossibletocompareourdesigntotheirs.InthisworktheobjectiveistoprovetheconceptofrealizingefficientanalogimplementationsofTurbodecodersinSiGetechnology,andtoinvestigate/evaluatetheprosandconsofsuchrealizationswhilekeepingthedesignprocedureandtheTurbodecoderinquiterealisticstandards.

3.DESIGNMETHODOLOGY

3.1TurboCodeStructure

TheTurboencoderisconstructedbytheparallelconcatenationoftwoormorerecursivesystematicconvolutionalcodes（RSC）,termedconstituentcodes.Theinputofthefirstencoderisnotpermuted.Theinputtotheotherencodersispermutedsothattheotherconstituentencodersarefedwiththeinterleavedanduncorrelatedformoftheinformationsequence.OurdesignreferstotheturboencoderthatcomprisestwoidenticalRSCcodesandonecyclicshiftinterleaver[24].TheRSCcodesusedaredescribedbythefollowinggeneratorpolynomial:

TheencodingprocessofanRSCcodecanberepresented

byatrellisdiagram,whichisdefinedbytherelevantgeneratorpolynomial.TheTurboencoderFig.1:

（I）Turboencoderstructure,（II）Onetrellissection,（III）theturbodecoderscheme.acceptsabitinformationsequenceuandprovidesasetofoutputsc=[u,p,q],wherepandqaretheparitybitsproducedbyRSC1andRSC2,respectively.Aftertheserializationoftheencoderoutputs,themodulatorformsandtransmitsthemthroughthechannel.InourcasetheBPSKmodulationschemeandtheAWGNmemorylesschannelmodelhavebeenemployed.Bothtrellisesareconsideredtruncatedattheend.TheTurbodecoderincorporatesaparallel-to-serial（P2S）interface,whichacceptsthecorrupted（bynoise）signalsandfeedsthemtothetwoAPPdecoders.Thetwodecodersexchangeiterativelyextrinsicinformation.Theextrinsicinformation,whichisareliabilitymeasureofeachcomponentdecoder’sestimateconcerningthetransmittedinformationsymbols,isbasedonthecorrespondingparitysequenceonly.ThisnegativefeedbackschemeisresponsiblefortheTurbodecoder’sstabilityandsuperiorperformance.Afteraspecifiednumberofiterationsthedecodermakesfinalhard-decisionsaboutthetransmittedinformationsequence.Figure1illustratestheTurboencoderwith1/3

rate,thetrellisdiagramoftheconstituentcodesand

theTurbodecoderarchitecture.

3.2FactorGraphRepresentation

TheTurboencodinganddecodingprocedurescanbeefficientlyrepresentedthroughabipartitegraphicalmodel,thefactorgraph,whichexpresseshowaglobalfunctionofseveralvariablesisfactoredintoaproductoflocalfunctions[3].Afactorgraphhasavariablenodexforeachvariable,afactornodefforeachlocalfunctionandanedgeconnectingavariablenodextoafactornodefifandonlyifxisanargumentoff.Thefinalcostfunction-inference（a-posterioriprobabilities）iscomputedbyperformingthesum-productalgorithmandthenode-updaterules[5].Figure2delineatesthefactorgraphforourTurbocodingscheme.ThevariablenodesYu,Yp,Yqarerepresentedbycirclesanddescribethechannelobservationsprovidede.g.bythematchedfilterofatypicalBPSKdemodulator.ThevariablenodesU,Q,Prepresentthetransmittedinformation（u）and