TMS320x2833x Multichannel Buffered Serial Port McBSP Reference Guide 第二章.docx

1、TMS320x2833x Multichannel Buffered Serial Port McBSP Reference Guide 第二章 第二章 McBSP OperationThis section addresses the following topics: 1. Data transfer process 2. Companding (compressing and expanding) data 3.Clocking and framing data 4.Frame phases 5.McBSP reception 6.McBSP transmission 7.Interru

2、pts and DMA events generated by McBSPs 2.1 Data Transfer Process of McBSPs Figure 2-1 shows a diagram of the McBSP data transfer paths. The McBSP receive operation is triple-buffered, and transmit operation is double-buffered. The use of registers varies, depending on whether the defined length of e

3、ach serial word is 16 bits. Figure 2-1. McBSP Data Transfer Paths2.1.1 Data Transfer Process for Word Length of 8, 12, or 16 Bits If the word length is 16 bits or smaller, only one 16-bit register is needed at each stage of the data transfer paths. The registers DRR2, RBR2, RSR2, DXR2, and XSR2 are

4、not used (written, read, or shifted). Receive data arrives on the DR pin and is shifted into receive shift register 1 (RSR1). Once a full word is received, the content of RSR1 is copied to receive buffer register 1 (RBR1) if RBR1 is not full with previous data. RBR1 is then copied to data receive re

5、gister 1 (DRR1), unless the previous content of DRR1 has not been read by the CPU or the DMA controller. If the companding feature of the McBSP is implemented, the required word length is 8 bits and receive data is expanded into the appropriate format before being passed from RBR1 to DRR1. For more

6、details about reception, see Section 2.5. Transmit data is written by the CPU or the DMA controller to data transmit register 1 (DXR1). If there is no previous data in transmit shift register (XSR1), the value in DXR1 is copied to XSR1; otherwise, DXR1 is copied to XSR1 when the last bit of the prev

7、ious data is shifted out on the DX pin. If selected, the companding module compresses 16-bit data into the appropriate 8-bit format before passing it to XSR1. After transmit frame synchronization, the transmitter begins shifting bits from XSR1 to the DX pin. For more details about transmission, see

8、Section 2.6. 2.1.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits If the word length is larger than 16 bits, two 16-bit registers are needed at each stage of the data transfer paths. The registers DRR2, RBR2, RSR2, DXR2, and XSR2 are needed to hold the most significant bits. Receive dat

9、a arrives on the DR pin and is shifted first into RSR2 and then into RSR1. Once the full word is received, the contents of RSR2 and RSR1 are copied to RBR2 and RBR1, respectively, if RBR1 is not full. Then the contents of RBR2 and RBR1 are copied to DRR2 and DRR1, respectively, unless the previous c

10、ontent of DRR1 has not been read by the CPU or the DMA controller. The CPU or the DMA controller must read data from DRR2 first and then from DRR1. When DRR1 is read, the next RBR-to-DRR copy occurs. For more details about reception, see Section 2.5. For transmission, the CPU or the DMA controller m

11、ust write data to DXR2 first and then to DXR1. When new data arrives in DXR1, if there is no previous data in XSR1, the contents of DXR2 and DXR1 are copied to XSR2 and XSR1, respectively; otherwise, the contents of the DXRs are copied to the XSRs when the last bit of the previous data is shifted ou

12、t on the DX pin. After transmit frame synchronization, the transmitter begins shifting bits from the XSRs to the DX pin. For more details about transmission, see Section 2.6. 2.2 Companding (Compressing and Expanding) Data Companding (COMpressing and exPANDing) hardware allows compression and expans

13、ion of data in either -law or A-law format. The companding standard employed in the United States and Japan is -law. The European companding standard is referred to as A-law. The specifications for -law and A-law log PCM are part of the CCITT G.711 recommendation. A-law and -law allow 13 bits and 14

14、 bits of dynamic range, respectively. Any values outside this range are set to the most positive or most negative value. Thus, for companding to work best, the data transferred to and from the McBSP via the CPU or DMA controller must be at least 16 bits wide. The -law and A-law formats both encode d

15、ata into 8-bit code words. Companded data is always 8 bits wide; the appropriate word length bits (RWDLEN1, RWDLEN2, XWDLEN1, XWDLEN2) must therefore be set to 0, indicating an 8-bit wide serial data stream. If companding is enabled and either of the frame phases does not have an 8-bit word length,

16、companding continues as if the word length is 8 bits. Figure 2-2 illustrates the companding processes. When companding is chosen for the transmitter, compression occurs during the process of copying data from DXR1 to XSR1. The transmit data is encoded according to the specified companding law (A-law

17、 or -law). When companding is chosen for the receiver, expansion occurs during the process of copying data from RBR1 to DRR1. The receive data is decoded to twos-complement format. Figure 2-2. Companding Processes2.2.1 Companding Formats For reception, the 8-bit compressed data in RBR1 is expanded t

18、o left-justified 16-bit data in DRR1. The receive sign-extension and justification mode specified in RJUST is ignored when companding is used. For transmission using -law compression, the 14 data bits must be left-justified in DXR1 and that the remaining two low-order bits are filled with 0s as show

19、n in Figure 2-3. Figure 2-3. -Law Transmit Data Companding FormatFor transmission using A-law compression, the 13 data bits must be left-justified in DXR1, with the remaining three low-order bits filled with 0s as shown in Figure 2-4. Figure 2-4. A-Law Transmit Data Companding Format2.2.2 Capability

20、 to Compand Internal Data If the McBSP is otherwise unused (the serial port transmit and receive sections are reset), the companding hardware can compand internal data. This can be used to: Convert linear to the appropriate -law or A-law format Convert -law or A-law to the linear format Observe the

21、quantization effects in companding by transmitting linear data and compressing and re-expanding this data. This is useful only if both XCOMPAND and RCOMPAND enable the same companding format. Figure 2-5 shows two methods by which the McBSP can compand internal data. Data paths for these two methods

22、are used to indicate: When both the transmit and receive sections of the serial port are reset, DRR1 and DXR1 are connected internally through the companding logic. Values from DXR1 are compressed, as selected by XCOMPAND, and then expanded, as selected by RCOMPAND. RRDY and XRDY bits are not set. H

23、owever, data is available in DRR1 within four CPU clocks after being written to DXR1. The advantage of this method is its speed. The disadvantage is that there is no synchronization available to the CPU and DMA to control the flow. DRR1 and DXR1 are internally connected if the (X/R)COMPAND bits are

24、set to 10b or 11b (compand using -law or A-law). The McBSP is enabled in digital loopback mode with companding appropriately enabled by RCOMPAND and XCOMPAND. Receive and transmit interrupts (RINT when RINTM = 0 and XINT when XINTM = 0) or synchronization events (REVT and XEVT) allow synchronization

25、 of the CPU or DMA to these conversions, respectively. Here, the time for this companding depends on the serial bit rate selected. Figure 2-5. Two Methods by Which the McBSP Can Compand Internal Data2.2.3 Reversing Bit Order: Option to Transfer LSB First Generally, the McBSP transmits or receives al

26、l data with the most significant bit (MSB) first. However, certain 8-bit data protocols (that do not use companded data) require the least significant bit (LSB) to be transferred first. If you set XCOMPAND = 01b in XCR2, the bit ordering of 8-bit words is reversed (LSB first) before being sent from

27、the serial port. If you set RCOMPAND = 01b in RCR2, the bit ordering of 8-bit words is reversed during reception. Similar to companding, this feature is enabled only if the appropriate word length bits are set to 0, indicating that 8-bit words are to be transferred serially. If either phase of the f

28、rame does not have an 8-bit word length, the McBSP assumes the word length is eight bits, and LSB-first ordering is done. 2.3 Clocking and Framing Data This section explains basic concepts and terminology important for understanding how McBSP data transfers are timed and delimited. 2.3.1 Clocking Da

29、ta is shifted one bit at a time from the DR pin to the RSR(s) or from the XSR(s) to the DX pin. The time for each bit transfer is controlled by the rising or falling edge of a clock signal. The receive clock signal (CLKR) controls bit transfers from the DR pin to the RSR(s). The transmit clock signa

30、l (CLKX) controls bit transfers from the XSR(s) to the DX pin. CLKR or CLKX can be derived from a pin at the boundary of the McBSP or derived from inside the McBSP. The polarities of CLKR and CLKX are programmable. In the example in Figure 2-6, the clock signal controls the timing of each bit transf

31、er on the pin. Figure 2-6. Example -Clock Signal Control of Bit Transfer Timing Note: The McBSP cannot operate at a frequency faster than the LSPCLK frequency. When driving CLKX or CLKR at the pin, choose an appropriate input clock frequency. When using the internal sample rate generator for CLKX an

32、d/or CLKR, choose an appropriate input clock frequency and divide down value (CLKDV) (i.e., be certain that CLKX or CLKR LSPCLK/2). 2.3.2 Serial Words Bits traveling between a shift register (RSR or XSR) and a data pin (DR or DX) are transferred in a group called a serial word. You can define how many bits are in a word. Bits coming in on the DR pin are held in RSR until RSR holds a full serial word. Only then is the word passed to RBR (and ultimately to the DRR). During transmission, XSR does not accept new data from DXR until a full serial word