基于FPGA的语音数字时钟系统.docx

1、基于FPGA的语音数字时钟系统基于FPGA的语音数字时钟系统设计1.设计要求：(1)计时功能：这是那个计时器设计的大体功能，每隔一分钟记一次时刻并在屏幕上显示出当前时刻。(2)闹钟功能：若是当前时刻与设置的闹钟时刻相同，则扬声器会发出报时声音。(3)设置新的计时器时刻：用户用数字键09输入新的时刻，然后按下TIME健确认。(4)设置新的闹钟时刻：用户用数字键09输入新的闹钟时刻，然后按下ALARM健确认。(5)显示所设置的闹钟时刻：在正常记时显示状态下，用户直接按下ALARM健，则显示器上显示已经设置好的闹钟时刻。2设计思路：操纵器命名为Alarm_controller，外部端口各个端口概念：

2、(1)Clk外部时钟信号(2)Reset复位信号(3)Alarm_botton闹钟信号，当其为高电平常，表示用户按下(4)Time_botton时刻信号，当其为高电平常，表示用户按下(5)Key键盘信号，当其为高电平常，表示用户按下09(6)Load_new_a读取新的闹钟时刻，高电平有效(7)Load_new_c操纵设置新的时刻，高电平有效(8)Show_new_time读取并显示新的时刻，高电平有效(9)Show_a当Show_new_time为低电平常，依照Show_a操纵当前是显示闹钟时刻仍是时钟时刻依照端口的设置和操纵要求，设定如下5个状态S0：闹钟正常计数状态S1：键盘输入状态，当

3、用户按下键盘，即进入此状态,当一段时刻后用户没有按下Alarm或Time确认，则自动返回S0状态S2：设定闹钟状态，当用户按完键盘，按下Alarm键时进入此状态S3：设按时刻状态，当用户按完键盘，按下Time键时进入此状态S4：显示闹钟时刻，当用户直接按下Alarm键时，进入此状态在S4状态下，用户按下Alarm键时钟即显示闹钟时刻，通过一段延时以后，时钟从头恢复S0状态。以下是程序流程表当前状态控制输入下一状态控制输出S0Key=1S1Show_new_time=1Alarm_botton=1S2Show_a=1elseS0NullS1Key=1S1Show_new_time=1Alarm_

4、botton=1S2Load_new_a=1Time_botton=1S3Load_new_c=1超时是S0Null否S1Show_new_time=1S2Alarm_botton=1S2Load_new_a=1elseS0NullS3Time_botton=1S3Load_new_c=1elseS0NullS4Alarm_botton=1S4Show_a超时是S0Null否S4Show_a并等待程序：程序包P_alarm封装概念library IEEE;use P_alarm is subtype t_digital is integer range 0 to 7; subtype t_sh

5、ort is integer range 0 to 65535; type t_clock_time is array(3 downto 0) of T_digital; type t_display is array(3 downto 0) of Std_logic_vector(6 downto 0); type seg7 is array(0 to 7) of Std_logic_vector(6 downto 0); constant Seven_seg:seg7:=(0000000001,-0 0000000010,-1 0000000100,-2 0000001000,-3 000

6、0010000,-4 0000100000,-5 0001000000,-6 00,-7 00,-8 00,-9);end package P_alarm;-程序包体封装终止library IEEE;use Alarm_contorller is port(Key,Alarm_botton,Time_botton,clk,reset:in std_logic; Load_new_a,Load_new_c,Show_new_time,Show_a:out std_logic);end Alarm_controller;ARCHITECTURE art of Alarm_controller is

7、 type t_state is(s0,s1,s2,s3,s4);-5种工作状态 constant key_timeout:t_short:=900;-键盘延不时刻 constant show_alarm_timeout:t_short:=900;-alarm jian yan shi 900ns signal curr_state:t_state;-zhuang tai ji dang qian zhuang tai wei signal next_state:t_state;-zhuang tai ji xia yi gong zuo wei signal counter_k:t_stat

8、e;-jian pan signal enable_count_k:std_logic;-jian pan chao shi yun xu signal count_k_end:std_logic;-jian pan chao shi signal counter_a:t_short;-alarm jian signal enable_count_a:std_logic;-alarm jian chao shi yun xu signal count_a_end:std_logic;-alarm jian chao shi jie shu begin p0:process(clk,reset)

9、 begin if reset=1then curr_state=s0; elsif rising_edge(clk)then curr_state=next_state; end if; end process; p1:process(Key,Alarm_botton,Time_botton,curr_state,count_a_end,count_k_end) begin -gei ge ge shu chu fu chu shi zhi next_state=curr_state; load_new_a=0; load_new_c=0; show_a=0; show_new_time=0

10、; enable_count_k=0; enable_count_a if(Key=1)then next_state=s1; Show_new_time=1; elsif(Alarm_botton=1)then next_state=s2; Show_a=1; else next_state if(key=1)then next_state=s1; Show_new_time=1; elsif(Alarm_botton=1)then next_state=s2; Load_new_a=1; elsif(Time_botton=1)then next_state=s3; Load_new_c=

11、1; else if(count_k_end=1)then next_state=s0; null; else next_state=s1; Show_new_time=1; end if; enable_count_k if(Alarm_botton=1)then next_state=s2; Load_new_a=1; else next_state if(Time_botton=1)then next_state=s3; Load_new_c=1; else next_state if(Alarm_botton=1)then next_state=s4; else if(count_a_

12、end=1)then next_state=s0; null; else next_state=s4; Show_a=1; end if; enable_count_a null; end case; end process; Count_key:process(Enable_count_k,clk) begin if (Enable_count_k=0)then Counter_k=0; count_k_end=key_tinmeout)then count_k_end=1; else counter_k=Counter_k+1; end if; end if; end process Co

13、unt_key; Count_alarm:process(Enable_count_a,clk) begin if(enable_count_a=1)then counter_a=0; count_a_end=show_alarm_timeout)then count_a_end=1; else counter_a=counter_a+1; end if; end if; end process Count_alarm;end art;二闹钟系统译码器设计1.设计思路：每次按下闹钟系统的数字键盘后产生一个数字所对应的10位二进制数据信号转换为1位十进制整数信号，作为小时，分钟计数的4个数字之一

14、。结构图 Decoder输入00000000010000000010000000010000000010000000010000输出01234输入00001000000001000000000000输出56789library IEEE;use decoder is port(keypad:in std_logic_vector(9 downto 0); value:out T_digital);end decoder;ARCHITECTURE art of decoder is begin with keypad select value=0 when 0000000001, 1 when

15、0000000010, 2 when 0000000100, 3 when 0000001000, 4 when 0000010000, 5 when 0000100000, 6 when 0001000000, 7 when 00, 8 when 00, 9 when 00, 0 when others; end art;三闹钟系统的移位寄放器的设计1.设计思路：在clk的上升沿同步下，将key端口的输入信号移入new_time端口的输出端口最低位，原有信息一次向左移动，最高位舍去，reset对输出端口new_time异步清零。 电路原理图library IEEE;use key_buffe

16、r isport(key:in t_digital; clk,reset:in std_logic; new_time:out t_clock_time);end key_buffer;ARCHITECTURE art of key_buffer is signal n_t:t_clock_time; process(clk,reset) begin if (reset=1)then n_t=(0,0,0,0); elsif(rising_edge(clk)then for i in 3 downto 1 loop-zuo huan yi n_t(i)=n_t(i-1); end loop;

17、n_t(0)=key; end if; end process; new_time=n_t; end art;四闹钟寄放器的设计1.设计思路：闹钟寄放器在时钟上升沿同步下，依照Load_new_a端口的输入信号操纵Alarm_time口的输出，当操纵信号为高电平常，把New_alarm_time端口的赋给alarm_time然后输出，reset端口输入信号对alarm_time端口的输出进行异步清零复位。电路原理图library IEEE;use Alarm_reg isport(clk,reset:in std_logic; new_alarm_time:in t_clock_time; l

18、oad_new_a:in std_logic; alarm_time:out std_logic);end Alarm_reg;ARCHITECTURE art of Alarm_reg is begin process(clk,reset) begin if(reset=1)then alarm_clock=(0,0,0,0); else if rising_edge(clk)then if load_new_a=1then alarm_time=new_alarm_time; elsif load_new_a=0then assert false reportuncertain load_

19、new_alarm control severity warning end if; end if; end if; end process; end art;五时刻计数器的设计1.设计思路：时刻计数器在时钟上升沿同步下，依照load_new_c端口的输入操纵信号操纵current_time口的输出，当操纵信号为高电平常，把new_current_time端口的值赋给current_time进行输出。当reset端口为高电平常，对current_time端口进行清零操作。Reset的优先级高于load_new_c,且当reset,load_new_c同时为低电平常，在时钟上升沿处，对curre

20、nt_time端口输出信号进行累加一次加1，并依照小时，分钟的进位规律进位。 Alarm_counterlibrary IEEE;use Alarm_counter isport(load_new_c:in std_logic; clk,reset:in std_logic; new_current_time:in t_clock_time; current_time:out t_clock_time);end Alarm_counter;ARCHITECTURE art of Alarm_counter is signal i_current_time:t_clock_time; begin

21、 process(clk,reset) variable c_t:t_clock_time; if reset=1then i_current_time=(0,0,0,0); elsif load_new_c=1then i_current_time=new_current_time; elsif rising_edge(clk)then if c_t(0)=9 then c_t(0):=c_t(0)+1; else c_t(0):=0; if c_t(1)6 then c_t(1):=c_t(1)+1; else c_t(1):=0; if c_t(3)2 then if c_t(2)=9

22、then c_t(2):=c_t(2)+1; else c_t(2):=0; c_t(3):=c_t(3)+1; end if; else c_t(2)3 then c_t(2):=c_t(2)+1; else c_t(2):=0; c_t(3):=0; end if; end if; end if; end if; i_current_time=c_t; end if; end process; current_time=i_current_time;end art;六闹钟系统显示驱动器1.设计思路:当show_new_time输入为高电平常，依照new_time端口输入的时刻数据，产生相应

23、的4个七段数码显示器的驱动数据，并在display端口输出该信号；当show_new_time为低电平常，判定show_a端口的输入电平，若是为高电平，则依照alarm_time端口输入的时刻数据，产生相应的4个七段数码显示器的驱动数据，并也在display端口输出。若show_a也为低电平，依照current_time端口的输入信号，对display端口驱动。当alarm_time端口的输入信号值与current_time端口的输入信号值相同时，sound_alarm端口的输出信号有效。反之无效 Display_driverlibrary IEEE;use display_driver is

24、 port(new_time:in t_clock_time; current_time:in t_clock_time; alarm_time:in t_clock_time; show_new_time:in std_logic; show_a:in std_logic; display:out t_display; sound_alarm:out std_logic);end display_driver;ARCHITECTURE art of display_driver is signal display_time:t_clock_time; begin process(new_ti

25、me,alarm_time,current_time,show_new_time,show_a) begin sound_loop:for i in alarm_timerange loop if(current_time(i)=alarm_time(i)then sound_alarm=1; else sound_alarm=0; end if; end loop sound_loop; if show_new_time=1then display_time=new_time; elsif show_a=1then display_time=alarm_time; elsif show_a=

26、0then display_time=current_time; else assert false report uncertain display_driver control! severity waring; end if; end process; disp:process(display_time) begin for i in display_timerange loop display(i)=seven_seg(display_time(i) end loop; end process; end art;七闹钟分频器1.设计思路：分频器，将clk_in的输入信号通过度频后交与c

27、lk_out当reset端口为高电平常，clk_out输出清零。 Fq_dividerlibrary IEEE;use fq_divider is port(clk_in,reset:in std_logic; clk_out:out std_logic);end fq_divider;ARCHITECTURE art of fq_divider is constant divide_period:t_short:=6000; begin process(clk_in,reset) variable cnt:t_short; begin if(reset=1)then cnt:=0; clk_

28、out=0; elsif rising_edge(clk)then if(cnt(divide_period/2)then clk_out=1; cnt:=cnt+1; elsif (cnt(divide_period-1)then clk_out=0 cnt:=cnt+1; else cnt:=0; end if; end if; end process; end art;八闹钟的整体组装1.设计思路：前面已经把闹钟的各个模块别离进行了编译封装，此刻开始整体组装。由于键盘解码和闹钟移位寄放器是一体的，且输出新的时刻或闹钟值，因此二者连为一体，再者，由于闹钟移位寄放器输出的新数据可能是时刻值也可能是闹钟值，因此输出口一分为2，别离接入时刻计数器，闹钟寄放器，又由于闹钟移位寄放器所输出的值要显示在led上，因此输出再引出一根线接到显示模块上。分