VHDL实现简易计算器.docx

1、VHDL实现简易计算器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity calculator is Port(clr,clk,dent,ch,set :in std_logic; add,sub,mul,div :in std_logic; outrange,minus :out logic; led1: out std_logic_vector(6 downto 0); led2: out std_logic_vector(6

2、 downto 0);led3: out std_logic_vector(6 downto 0);led4: out std_logic_vector(6 downto 0); end calculator;architecture Behavioral of calculator issignal sec_1_10,sec1 :std_logic;signal get,minus_sig :integer range 0 to 3;signal choose : integer range 0 to 5;signal chose : integer range 0 to 7;signal

3、L2,LL2,LLL2,LLLL2 : integer range 0 to 10;signal L1,LL1,LLL1,LLLL1: integer range 0 to 10;signal L,LL,LLL,LLLL : integer range 0 to 10;signal nn : integer range 0 to 9999;signal bi : integer range 0 to 20000;begin分频模块 process(clr,clk)variable c: integer range 0 to 10;beginif clr=0 then c:=0;elsif ri

4、sing_edge(clk) thenif c5 then sec1=1;else sec1=0;end if;end process;process(clr,clk)variable c : integer range 0 to 3200000;begin if clr=0 then c:=0;elsif rising_edge(clk) thenif c1600000 then sec_1_10=1;else sec_1_10=0;end if;end process;键控模块process (sec_1_10,clr,mul,div,sub,add,set)variable cc,dd

5、: std_logic;variable p,pp : integer range 0 to 3;variable c : integer range 0 to 5;variable m : integer range 0 to 7;variable d,e,f,g : integer range 0 to 9;variable ee : integer range 0 to 90;variable ff : integer range 0 to 900;variable gg : integer range 0 to 9000;beginif clr=0 or (mul=0 or div=0

6、 or sub=0 or add=0)and set=1 and ch=1)then c:=0; d:=0; e:=0; f:=0; g:=0;ee:=0; ff:=0; gg:=0; m:=0; p:=0; cc:=0; dd:=0;pp:=0;elsif rising_edge(sec_1_10) thenif dent=1 thenif m7 then m:=m+1;else m:=7;end if;elsif set=0 and add=0 then dd:=1;elsif dd=1 thenif pp3 then pp:=pp+1;else pp:=0;dd:=0;end if;el

7、sif div=0and set=0 then cc:=1;elsif cc=1 thenif p3 then p:=p+1;else p:=3;cc:=0;end if;elsif ch=0 thenif c5 then c:=c+1;else c:=1;end if;elsif c=2 and set=0thenif d9 then d:=d+1;else d:=0;end if;elsif c=3 and set=0thenif e9 then e:=e+1;ee:=ee+10;else e:=0;ee:=0;end if;elsif c=4 and set=0thenif f9 the

8、n f:=f+1;ff:=ff+100;else f:=0;ff:=0;end if;elsif c=5 and set=0thenif g9 then g:=g+1;gg:=gg+1000;else g:=0;gg:=0;end if;else null;end if;end if;choose=c;L1=d;LL1=e; LLL1=f; LLLLL1=g;nn=d+ee+ff+gg;chose=m;get=p;minus_sig=pp;end process;运算及存储模块process (clr,sec1,bi)variable min mmin : std_logic;variable

9、 ad,sb,mu,dv :std_logic_vector(1 downto 0);variable c,d, f,g,m : integer range 0 to 20000;beginif clr=0 then min:=1; c:=0; d:=0; f:=0; g:=0;bi=0;sb:=“00”;ad :=“00”;mu :=“00”; dv:=“00”;outrange =1;elsif rising_edge(sec1) thenif set=0 and mul=0then mmin:=min;if ad :=“00”and sb :=“00”and mu:=“00” and d

10、v:=“00” then m:=nn;else m:=bi;end if;elsif set=0 and div=0 then bi=m;d:=m;min:=mmin;ad:=“10”；elsif minus_sig=3 then min:=not(min);elsif sub=0 and set=1 then sb:=“01”;ad :=“00”;mu :=“00”; dv:=“00”;elsif add=0 and set=1 then ad:=“01”;sb :=“00”;mu :=“00”; dv:=“00”;elsif mul=0 and set=1 then mu:=“01”;ad

11、 :=“00”;sb :=“00”; dv:=“00”;f:=0;g:=0;elsif div=0 and set=1 then dv:=“01”;ad :=“00”;sb :=“00”; mu:=“00”;f:=0; elsif dent=0 and ad=“00” and sb=“00” and mu=“00”and dv=“00”then d：=nn;bi=c then d:=d-c;bi=d;else min:=0;bi=c-d;end if;elsif (c+d)10000 then sb:=“10”；bi=(c+d);else outrange=0；bi=0;end if;elsi

12、f ad=“01” and dent=1then c:=nn;if min=1then ad:=“10”；if (c+d)10000 then d：=（c+d）；bi=d;else outrange=0；bi=0;end if;elsif cd then bi=d-c;ad:=“10”;else min:=1；bi=c-d;ad:=“10”；end if;elsif mu=“01” and dent=1 then c:=nn;if c=0 or d=0 then bi=0;elsif f9999 then bi=0;outrange=0;else f:=f+1;end if;else bi=g; mu:=“10”；end if;elsif dv=“01” and dent=1 then c:=nn;if c=0 then bi=0;outrange=0；elsif c=1 then bi=c then if f20000 then d:=d-c;f:=f+1;else null;end if;elsif dc/2 then bi=f;dv:=“10”；else bi=f+1；dv:=“10”；end if;else null;end if;end if;minus999 then cc:=cc+1;bb:=bb-1000;elsif