杭电计组实验10实现RIJ型指令的CPU设计实验精编版.docx

1、杭电计组实验10实现RIJ型指令的CPU设计实验精编版实验报告 2018 年 6 月 9 日 成绩： 姓名阳光男学号16041321班级16052317专业计算机科学与技术课程名称计算机组成原理与系统结构试验任课老师张翔老师指导老师张翔老师机位号默认实验序号10实验名称实验十 实现R-I-J型指令的CPU设计实验实验时间2018/6/9实验地点1教221实验设备号个人电脑、Nexys3开发板 一、实验程序源代码顶层RI型指令CPU模块测试文件：module test; / Inputs reg rst; reg clk_100MHz; reg clk; / Outputs wire ZF; w

2、ire OF; wire 31:0 F; wire 31:0 M_R_Data; wire 31:0 PC; / Instantiate the Unit Under Test (UUT) TOP_RIJ_CPU uut ( .rst(rst), .clk_100MHz(clk_100MHz), .clk(clk), .ZF(ZF), .OF(OF), .F(F), .M_R_Data(M_R_Data), .PC(PC) ); initial begin / Initialize Inputs rst = 0; clk_100MHz = 0; clk = 0; / Wait 100 ns f

3、or global reset to finish #100; / Add stimulus here forever begin #2; clk=clk; #10; clk_100MHz=clk_100MHz; end end endmodule顶层LED验证模块module TOP_LED(clk_100MHz,oclk,rst,SW,LED);input clk_100MHz;input oclk,rst;input 3:0SW;output reg7:0LED;wire rclk;wire ZF,OF;wire 31:0F;wire 31:0M_R_Data;wire 31:0PC;x

4、iaodou doudong(clk_100MHz,oclk,rclk);TOP_RIJ_CPU(rst,clk_100MHz,rclk,ZF,OF,F,M_R_Data,PC);always(*)begincase(SW)4b0000:LED=F7:0;4b0001:LED=F15:8;4b0010:LED=F23:16;4b0011:LED=F31:24;4b0100:LED=M_R_Data7:0;4b0101:LED=M_R_Data15:8;4b0110:LED=M_R_Data23:16;4b0111:LED=M_R_Data31:24;4b1000:begin LED7:2=0;

5、LED1=OF;LED0=ZF;end4b1100:LED=PC7:0;4b1101:LED=PC15:8;4b1110:LED=PC23:16;4b1111:LED=PC31:24;default:LED=0;endcaseendendmodule顶层RIJ型指令CPU验证模块：module TOP_RIJ_CPU(input rst,input clk_100MHz,input clk,output ZF,output OF,output 31:0F,output 31:0M_R_Data,output 31:0PC);wire Write_Reg;wire 31:0Inst_code;w

6、ire 4:0rs;wire 4:0rt;wire 4:0rd;wire 31:0rs_data;wire 31:0rt_data;wire 31:0rd_data;wire 31:0imm_data;/被扩展的立即数wire 15:0imm;/wire rd_rt_s;wire 1:0w_r_s;wire imm_s;/判断是否需要扩展wire rt_imm_s;/B端选择rt或者是扩展后的immwire Mem_Write;/wire alu_mem_s;wire 1:0wr_data_s;wire 31:0W_Addr;wire 31:0W_Data;wire 31:0R_Data_A;

7、wire 31:0R_Data_B;wire 31:0F;wire 31:0ALU_B;/B端口数据wire 2:0ALU_OP;wire 1:0PC_s;wire 31:0PC_new;wire 31:0PC;wire 25:0address;pc pc_connect(clk,rst,PC_s,R_Data_A,imm_data,address,Inst_code,PC);OP_YIMA op(Inst_code,ALU_OP,rs,rt,rd,Write_Reg,imm,imm_s,rt_imm_s,Mem_Write,address,w_r_s,wr_data_s,PC_s,ZF);a

8、ssign W_Addr=(w_r_s1)?5b11111:(w_r_s0)?rt:rd);assign imm_data=(imm_s)?16imm15,imm:161b0,imm;Register_file R_connect(rs,rt,W_Addr,Write_Reg,W_Data,clk,rst,R_Data_A,R_Data_B);assign ALU_B=(rt_imm_s)?imm_data:R_Data_B;ALU ALU_connect(R_Data_A,ALU_B,F,ALU_OP,ZF,OF);RAM_B Data_Mem ( .clka(clk_100MHz), /

9、input clka .wea(Mem_Write), / input 0 : 0 wea .addra(F5:0), / input 5 : 0 addra .dina(R_Data_B), / input 31 : 0 dina .douta(M_R_Data) / output 31 : 0 douta); assign W_Data=(wr_data_s1)?PC_new:(wr_data_s0)?M_R_Data:F);endmodulePC取指令模块：module pc(input clk,input rst,input 1:0PC_s,input 31:0R_Data_A,inp

10、ut 31:0imm_data,input 25:0address,output 31:0Inst_code,output 31:0PC);reg 31:0PC;wire31:0PC_new;initial PC=32h00000000;Inst_ROM Inst_ROM1 ( .clka(clk), .addra(PC7:2), .douta(Inst_code) );assign PC_new=PC+4;always(negedge clk or posedge rst)begin if(rst) PC=32h00000000; else begin case(PC_s) 2b00:PC=

11、PC_new; 2b01:PC=R_Data_A; 2b10:PC=PC_new+(imm_data2); 2b11:PC=PC_new31:28,address,2b00; endcaseendendendmoduleOP指令功能译码模块：module OP_YIMA(inst,ALU_OP,rs,rt,rd,Write_Reg,imm,imm_s,rt_imm_s,Mem_Write,address,w_r_s,wr_data_s,PC_s,ZF);input 31:0inst;output reg2:0ALU_OP;output reg4:0rs;output reg4:0rt;outp

12、ut reg4:0rd;output reg Write_Reg;output reg15:0imm;/output reg rd_rt_s;output reg imm_s;output reg rt_imm_s;output reg Mem_Write;output reg 25:0address;output reg1:0 w_r_s;output reg1:0 wr_data_s;output reg1:0 PC_s;input ZF;always(*)begin/-处理R型指令-if(inst31:26=6b000000)begin rd=inst15:11; rt=inst20:1

13、6; rs=inst25:21; /alu_mem_s=0; wr_data_s=2b00; Mem_Write=0; /rd_rt_s=0; w_r_s=2b00; rt_imm_s=0;case(inst5:0)6b100000:begin ALU_OP=3b100;Write_Reg=1;PC_s=2b00;end6b100010:begin ALU_OP=3b101;Write_Reg=1;PC_s=2b00;end6b100100:begin ALU_OP=3b000;Write_Reg=1;PC_s=2b00;end6b100101:begin ALU_OP=3b001;Write

14、_Reg=1;PC_s=2b00;end6b100110:begin ALU_OP=3b010;Write_Reg=1;PC_s=2b00;end6b100111:begin ALU_OP=3b011;Write_Reg=1;PC_s=2b00;end6b101011:begin ALU_OP=3b110;Write_Reg=1;PC_s=2b00;end6b000100:begin ALU_OP=3b111;Write_Reg=1;PC_s=2b00;end6b001000:begin ALU_OP=3b100;Write_Reg=0;PC_s=2b01;endendcaseend/-I型立

15、即数寻址指令-if(inst31:29=3b001)beginimm=inst15:0;rt=inst20:16;rs=inst25:21;Mem_Write=0;/rd_rt_s=1;rt_imm_s=1;/alu_mem_s=0;w_r_s=2b01;Write_Reg=1;wr_data_s=2b00;case(inst31:26)6b001000:begin imm_s=1;ALU_OP=3b100;end6b001100:begin imm_s=0;ALU_OP=3b000;end6b001110:begin imm_s=0;ALU_OP=3b010;end6b001011:begi

16、n imm_s=0;ALU_OP=3b110;endendcaseend/-处理I型取数/存数指令-if(inst31:30=2b10)&(inst28:26=3b011)beginimm=inst15:0;rt=inst20:16;/rt寄存器rs=inst25:21;/rs寄存器/rd_rt_s=1;/rt作为目的存储器rt_imm_s=1;/imm作为源操作数imm_s=1;w_r_s=2b01;wr_data_s=2b01;PC_s=2b00;case(inst31:26)6b100011:begin Mem_Write=0; Write_Reg=1;ALU_OP=3b100;end6

17、b101011:begin Mem_Write=1; Write_Reg=0;ALU_OP=3b100;endendcaseend/-处理I型跳转指令-if(inst31:27=5b00010)begin imm=inst15:0; rt=inst20:16;/rt rs=inst25:21;/rs case(inst31:26) 6b000100:begin rt_imm_s=0;ALU_OP=3b101;Write_Reg=0;Mem_Write=0; PC_s=(ZF?2b10:2b00);end 6b000101:begin rt_imm_s=0;ALU_OP=3b101;Write_

18、Reg=0;Mem_Write=0; PC_s=(ZF?2b00:2b10);end endcase end /-处理J型跳转指令- if(inst31:27=5b00001) begin address=inst25:0; case(inst31:26) 6b000010:begin w_r_s=2b00;Write_Reg=0;Mem_Write=0;PC_s=2b11;end 6b000011:begin w_r_s=2b10;wr_data_s=2b10;Write_Reg=1;Mem_Write=0;PC_s=2b11;end endcase end endendmodule寄存器堆

19、模块：module Register_file(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data_B);input 4:0R_Addr_A;input 4:0R_Addr_B;input 4:0W_Addr;input Write_Reg;input 31:0W_Data;input Clk;input Reset;output 31:0R_Data_A;output 31:0R_Data_B;reg 31:0REG_Files0:31;reg 5:0i;initial/仿真过程中的初始化begin for(

20、i=0;i=31;i=i+1) REG_Filesi=0;endassign R_Data_A=REG_FilesR_Addr_A;assign R_Data_B=REG_FilesR_Addr_B;always(posedge Clk or posedge Reset)begin if(Reset) for(i=0;i=31;i=i+1) REG_Filesi=0; else if(Write_Reg&W_Addr!=0) REG_FilesW_Addr=W_Data; end endmoduleALU运算模块：module ALU(A,B,F,ALU_OP,ZF,OF);input 31:

21、0A,B;input 2:0ALU_OP;output reg ZF,OF;output reg31:0F;reg C32;always(*)begin OF=1b0; C32=1b0; case(ALU_OP) 3b000:F=A&B; 3b001:F=A|B; 3b010:F=AB; 3b011:F=(AB); 3b100:begin C32,F=A+B;OF=A31B31F31C32;end 3b101:begin C32,F=A-B;OF=A31B31F31C32;end 3b110: if(AB) F=1; else F=0; 3b111:F=BA; endcase if(F=0)

22、ZF=1; else ZF=0; end endmodule二、仿真波形三、电路图 顶层电路模块 顶层电路内部结构：四、引脚配置（约束文件）NET LED7 LOC = T11;NET LED6 LOC = R11;NET LED5 LOC = N11;NET LED4 LOC = M11;NET LED3 LOC = V15;NET LED2 LOC = U15;NET LED1 LOC = V16;NET LED0 LOC = U16;NET SW3 LOC = M8;NET SW1 LOC = T9;NET SW0 LOC = T10;NET clk_100MHz LOC = V10;N

23、ET oclk LOC = C9;NET rst LOC = C4;NET SW2 LOC = V9;五、思考与探索（1）R-I-J型指令CPU实验结果记录表序号 指令 执行结果 标志 结论 1 00004020 $8=0000_0000 0 0 正确 2 00004820 $9=0000_0000 0 0 正确 3 200a0014 $10=0000_0014 0 0 正确 4 8d2b0010 $11=0000_0010 0 0 正确 5 010b4020 $8=0000_2222 0 0 正确 6 21290004 $9=0000_0004 0 0 正确 7 214affff $10=000_0013 0 0 正确 8 11400001 判断：$10不为0 0 0 正确 9 08000003 返回去执行地址为 0 0 正确 0000_0010的指令， 即序号4：8d2b0010 10 ac0b0030 存储器地址：0000_0030 0 0 正确