LCD万年历程序.docx

1、LCD万年历程序-本程序初始化与数据写入LCD的系统频率不变,-这样受初始化延时限制整体时钟不快，但能满足要求。LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.all;ENTITY sent_data_to_lcd IS PORT( Fu_Wei: IN STD_LOGIC; clk_1MHz: in STD_LOGIC; clk_10KHz: in STD_LOGIC; clk_50Hz: in STD_LOGIC; clk_1Hz: in STD_LO

2、GIC; position: in std_logic; number: in std_logic; display: in std_logic; RS: out STD_LOGIC; RW: out STD_LOGIC; E: out STD_LOGIC; D: out STD_LOGIC_vector(7 downto 0) ); end; architecture doit of sent_data_to_lcd is signal clk10KHz,E1: std_logic;signal delay: natural range 0 to 260;constant C40ms: na

3、tural:=200;-延时40ms应需5KHz时钟脉冲个数为：C40ms=40/T_5=40/0.2=200constant C10ms: natural:=50; -E1一次变化一个周期需要2msconstant End_Time: natural:=260;-10位秒表信号与常量定义-signal counter: natural range 0 to 80;signal position_temp,number_temp: natural range 0 to 10;signal ms_sec: natural range 0 to 1000;signal us_sec: natura

4、l range 0 to 1000;signal T_sec,T_min: natural range 0 to 60;-万年历信号与常量定义-signal year: natural range 0 to 9999;signal month: natural range 0 to 12;signal date: natural range 0 to 31;signal D_sec,D_min: natural range 0 to 60;signal D_hour: natural range 0 to 24; -constant C5KHz: natural:=2000;-constant

5、 C1MHz: natural:=20;begin -分频产生5KHz信号clk5KHz-根据初始化是需要求：POWER ON-Wait time40ms-Function Set-Wait time100us- -Function Set-Wait time37us-Display ON/OFF Control-Wait time100us- -Display Clear，Wait -time10ms-Enter mode set-Initialization end。- 5KHz的T_5=0.2ms=200usprocess(position) begin if rising_edge(p

6、osition) then if position_temp9 then position_temp=position_temp+1; else position_temp=0; end if; end if; end process;process(number) begin if rising_edge(number) then if number_temp9 then number_temp=number_temp+1; else number_temp=0; end if; end if; end process;-万年历计算模块- year=year4 & year3 & year2

7、 & year1;- month=month2 & month1;- date=date2 & dare1;process(clk_1Hz) begin- if Fu_Wei=0 then- ms_sec1=0;ms_sec2=0;ms_sec3=0;- us_sec1=0;us_sec2=0;us_sec3=0;- elsif display=0 then - ms_sec1=ms_sec1;ms_sec2=ms_sec2;ms_sec3=ms_sec3;- us_sec1=us_sec1;us_sec2=us_sec2;us_sec3 0 then- if number_temp =0 t

8、hen ms_sec2=10;- else ms_sec2=number_temp;- end if;- end if; if rising_edge(clk_1Hz) then if D_sec 59 then -D_sec19 then D_sec=D_sec+1; -D_sec1=us_sec1+1; else D_sec=0;-D_sec1=0; if D_min59 then -D_sec25 then D_min=D_min+1; -D_sec2=D_sec2+1; else D_min=0;-D_sec2=0; if D_hour23 then -D_min19 then D_h

9、our=D_hour+1; -D_min1=D_min1+1; else D_hour=0; -D_min1=0; if (month=1 or month=3 or month=5 or month=7 or month=8 or month=10 or month=12) then if date31 then date=date+1; else date=1; end if; elsif (month=4 or month=6 or month=9 or month=11) then if date30 then date=date+1; else date=1; end if; els

10、if month=2 then if (year/4=0 or (year/100=0 and year/400=0)then if date29 then date=date+1; else date=5; end if; else if date28 then date=date+1; else date=1; end if; end if; end if; if date=1 then if month12 then month=month+1; else month=1; if year9999 then year=year+1; else year=2010; end if; end

11、 if; end if; end if; end if; end if; end if; end process;-10位秒表计算模块- process(clk_1MHz) begin if Fu_Wei=0 then us_sec=0;ms_sec=0; T_sec=0;T_min=0; elsif display=0 then us_sec=us_sec;ms_sec=ms_sec; T_sec=T_sec;T_min 0 then - if number_temp =0 then ms_sec2=10; - else ms_sec2=number_temp; - end if; -end

12、 if; elsif rising_edge(clk_1MHz) then if us_sec999 then us_sec=us_sec+1; else us_sec=0; if ms_sec999 then ms_sec=ms_sec+1; else ms_sec=0; if T_sec59 then T_sec=T_sec+1; else T_sec=0; if T_min59 then T_min=T_min+1; else T_min=0; end if; end if; end if; end if; end if; end process;-定时器-process(clk_10K

13、Hz,Fu_Wei) begin if Fu_Wei=0 then delay=0; elsif rising_edge(clk_10KHz) then if delay=End_Time then delay=delay; else delay=delay+1; end if; end if;end process;-从初始化第一条数据Function Set，到最后一条数据Display Clear为4个E1周期,-共需系统时钟10MHz 8个周期 clk10KHz=0 when delayC40ms and delay(C40ms+8) and delay=(C40ms+8+C10ms)

14、else-再延时10ms clk_10KHz;-LCD时序控制部分-LCD输出时序处理：RS=1写数据，RS=0写指令。RW=1读数据，RW=0写指令。-E下降沿时输入LCD的数据D有效，E最小周期为1200ns。 process(clk10KHz,Fu_Wei)-clk_5KHz begin if rising_edge(clk10KHz) then E1=not E1; if E1=1 then E=1; if counter38 then counter=counter+1; else counter=6; end if; else E=0; end if; end if; end pr

15、ocess; p2: process(counter) begin if (counter8 or counter=22) then rs=0; rw7 then rs=1; rw D D DD D D D DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDnull; end case; END PROCESS;END doit;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.numeric_std.all;entity divide

16、d_clock is port( clk_20MHz: in std_logic; clk_1MHz: out std_logic; clk_10KHz: out std_logic; clk_50Hz: out std_logic; clk_1Hz: out std_logic ); end; architecture doit of divided_clock is signal clk1M,clk10KHz,clk50Hz,clk1Hz: std_logic; signal count1MHz: natural range 0 to 20;-20MHz/1MHz=20 signal co

17、unt10KHz: natural range 0 to 1000;-20MHz/10KHz=1000 signal count50Hz: natural range 0 to 400000;-20MHz/50KHz=400000 signal count1Hz: natural range 0 to 20000000;-20MHz/1Hz=20000000 constant c_1MHz: natural :=20; constant c_10KHz: natural :=1000; constant c_50Hz: natural :=400000; constant c_1Hz: nat

18、ural :=20000000; beginprocess(clk_20MHz)begin if rising_edge(clk_20MHz) then if count1MHz(c_1MHz-1) then -50 then count1MHz=count1MHz+1; else count1MHz=0; end if; if count1MHz(c_1MHz/2-1) then -1 then clk1M=0; else clk1M=1; end if; end if;end process;process(clk_20MHz)begin if rising_edge(clk_20MHz)

19、 then if count10KHz(c_10KHz-1) then -50 then count10KHz=count10KHz+1; else count10KHz=0; end if; if count10KHz(c_10KHz/2-1) then -1 then clk10KHz=0; else clk10KHz=1; end if; end if;end process;process(clk_20MHz)begin if rising_edge(clk_20MHz) then if count50Hz(c_50Hz-1) then -50 then count50Hz=count

20、50Hz+1; else count50Hz=0; end if; if count50Hz(c_50Hz/2-1) then -1 then clk50Hz=0; else clk50Hz=1; end if; end if;end process;process(clk_20MHz)begin if rising_edge(clk_20MHz) then if count1Hz(c_1Hz-1) then -50 then count1Hz=count1Hz+1; else count1Hz=0; end if; if count1Hz(c_1Hz/2-1) then -1 then clk1Hz=0; else clk1Hz=1; end if; end if;end process; clk_1MHz=clk1M; clk_10KHz=clk10KHz; clk_50Hz=clk50Hz; clk_1Hz=clk1Hz; end doit;