数字钟实验代码.docx

1、数字钟实验代码 数字钟实验代码电信0902 张超 u200913639module counter24( input wire cp, input wire ncr, input wire en, output reg 3:0 cnth, output reg 3:0 cntl); always (posedge cp or negedge ncr)begin if (ncr) begin cnth,cntl=8h00;/如果清零符号ncr为低电位，则清零 end else if(en) begin cnth,cntl2)|(cntl9)|(cnth=2)&(cntl=3) begin cnt

2、h,cntl=8h00;/如果十位大于二，或各位大于九，或达到二十三则清零重新计数。 end else if(cnth=2)&(cntl3) begin cnth=cnth; cntl=cntl+1b1;/十位等于二并且各位小于三时，则各位计数加一 end else if(cntl=9) begin cnth=cnth+1b1; cntl=4b0000;/另外，十位小于二，各位计数为九时，各位清零，十位进一位 end else begin cnth=cnth;cntl=cntl+1b1;/其他的情况则各位计数 endendendmodulemodule counter10( input wir

3、e cp, input wire ncr, input wire en, output reg3:0 q); always (posedge cp or negedge ncr)begin if(ncr) begin q=4b0000;/如果清零符号ncr为低电位，则清零 end else if(en) begin q=q;/如果en为低电位则保持 end else if(q=4b1001) begin q=4b0000; end else begin q=q+1b1; endend endmodulemodule counter6( input wire cp, input wire ncr

4、, input wire en, output reg3:0 q); always(posedge cp or negedge ncr)begin if(ncr) begin q=4b0000; end else if(en) begin q=q; end else if(q=4b0101) begin q=4b0000; end else begin q=q+1b1; endendendmodulemodule top_clock( input wire cp, input wire ncr, input wire en, input wire adj_min, input wire adj

5、_hour, output wire 7:0 hour, output wire 7:0 minute, output wire 7:0second); supply1 vcc; wire minl_en; wire minh_en; wire hour_en;counter10 u1( .q(second3:0), .ncr(ncr), .en(en), .cp(cp);counter6 u2( .q(second7:4), .ncr(ncr), .en(second3:0=4h9), .cp(cp);/秒的个位调用十进位，十位用六进制assign minl_en = adj_min?(se

6、cond=8h59):vcc;assign minh_en = (adj_min&(minute3:0=4h9)|(minute3:0=4h9) &(second=8h59);counter10 u3( .q(minute3:0), .ncr(ncr), .en(minl_en), .cp(cp);counter6 u4( .q(minute7:4), .ncr(ncr), .en(minh_en), .cp(cp);/分的个位用十进制，十位用六进制assign hour_en = adj_hour?(minute=8h59)&(second=8h59):vcc;counter24 u5( .

7、cnth(hour7:4), .cntl(hour3:0), .ncr(ncr), .en(hour_en), .cp(cp);endmodulemodule freq( input wire clk50M, input wire rst, output reg clk1Hz);parameter CNT_1HZ = 50000000;reg31:0 cnt;always (posedge clk50M or posedge rst)begin if(rst) begin clk1Hz = 0; cnt = CNT_1HZ -1) begin cnt = 0; end else begin c

8、nt = cnt + 1; end if(cnt CNT_1HZ/2) begin clk1Hz = 0;/前一半计数为低电位 end else if(cnt CNT_1HZ - 1) begin clk1Hz = 1;/后一半计数为高电位 end endendendmodulemodule disp( input wire clk50M, input wire3:0 HexCode, output wire7:0 SegmentCode); reg7:0 Segment; assign SegmentCode7:0 = Segment7:0;always (posedge clk50M)be

9、gin begin case(HexCode) 4h0: begin Segment = 8h3F; end 4h1: begin Segment = 8h06; end 4h2: begin Segment = 8h5B; end 4h3: begin Segment = 8h4F; end 4h4: begin Segment = 8h66; end 4h5: begin Segment = 8h6D; end 4h6: begin Segment = 8h7D; end 4h7: begin Segment = 8h07; end 4h8: begin Segment = 8h7F; e

10、nd 4h9: begin Segment = 8h6F; end default: begin Segment = 8h00; end endcase endendendmodulemodule radio( input wire7:0 minute, input wire7:0 second, output reg alarm_radio);always (minute or second)begin if(minute = 8h59) begin case(second) 8h51, 8h53, 8h55, 8h57, 8h59:alarm_radio = 1b1; default:al

11、arm_radio = 1b0; endcase /在51、53、55、57、59秒时LED灯各亮一次 end else alarm_radio = 1b0;endendmodulemodule bell( input wire cp, input wire sethrkey, input wire setminkey, input wire ctrlbell, input wire7:0 hour, input wire7:0 minute, input wire7:0 second, output wire alarm_clock, output wire7:0 set_hr,set_mi

12、n); supply1 vdd; wire hrh_equ; wire hrl_equ; wire minh_equ; wire minl_equ; wire time_equ; counter10 su1( .q(set_min3:0), .ncr(vdd), .en(setminkey), .cp(cp);counter6 su2( .q(set_min7:4), .ncr(vdd), .en(set_min3:0 = 4h9), .cp(cp);counter24 su3( .cnth(set_hr7:4), .cntl(set_hr3:0), .ncr(vdd), .en(sethrk

13、ey), .cp(cp);assign hrh_equ = (set_hr7:4=hour7:4);assign hrl_equ = (set_hr3:0=hour3:0);assign minh_equ = (set_min7:4=minute7:4);assign minl_equ = (set_min3:0=minute3:0);assign time_equ = (hrh_equ&hrl_equ&minh_equ&minl_equ);assign alarm_clock = ctrlbell? time_equ:1b0;endmodulemodule complete_clock( i

14、nput wire clk50M, input wire ncr, input wire mode, input wire oe, input wire en, input wire adj_min, input wire adj_hour, input wire sethrkey, input wire setminkey, input wire ctrlbell, output wire 7:0 qa, output wire 7:0 qb, output wire 7:0 qc, output wire 7:0 qd, output wire alarm); wire 7:0 hour;

15、 wire 7:0 minute; wire 7:0 second; wire cp; wire 3:0 da0; wire 3:0 da1; wire 3:0 da2; wire 3:0 da3; wire alarm_radio; wire alarm_clock; wire 7:0 set_hr; wire 7:0 set_min; assign da0 = mode ? set_min3:0 : (oe ? minute3:0 : second3:0); assign da1 = mode ? set_min7:4 : (oe ? minute7:4 : second7:4); ass

16、ign da2 = mode ? set_hr3:0 : (oe ? hour3:0 : minute3:0); assign da3 = mode ? set_hr7:4 : (oe ? hour7:4 : minute7:4); assign alarm = alarm_radio | alarm_clock; top_clock top1( .hour(hour), .minute(minute), .second(second), .cp(cp), .ncr(ncr), .en(en), .adj_min(adj_min), .adj_hour(adj_hour); disp disp

17、1 ( .clk50M(clk50M), .HexCode(da3), .SegmentCode(qa); disp disp2 ( .clk50M(clk50M), .HexCode(da2), .SegmentCode(qb) ); disp disp3 ( .clk50M(clk50M), .HexCode(da1), .SegmentCode(qc);disp disp4( .clk50M(clk50M), .HexCode(da0), .SegmentCode(qd);freq freq_INST( .clk50M(clk50M), .rst(ncr), .clk1Hz(cp);radio ra1( .minute(minute), .second(second), .alarm_radio(alarm_radio);bell be1( .cp(cp), .sethrkey(sethrkey), .setminkey(setminkey), .ctrlbell(ctrlbell), .hour(hour), .minute(minute), .second(second), .alarm_clock(alarm_clock), .set_hr(set_hr), .set_min(set_min);endmodule