NRF24L01LINUX驱动程序SPI驱动MINI2440.docx

1、NRF24L01LINUX驱动程序SPI驱动MINI2440包括LINUX下驱动程序和应用程序，MINI2440亲测可用#include #include #include #include #include #include #include #include #include #include unsigned char TxBuf32 = 0x00;int main(void) int fd = -1; int count = 1; /fd = open(/dev/nrf24l01, 0); fd = open(/dev/NRF24l01, O_RDWR); if(fd 0) perro

2、r(Cant open /dev/nrf24l01 n); exit(1); printf(open /dev/nrf24l01 success n); while(count = 5) write(fd, &TxBuf , sizeof(TxBuf); printf(Sending %d time n, count); usleep(100*1000); count+; close(fd);/#include /#include #include #include #include #include #include #include /#include /#include #include

3、 /#include /#include /typedef unsigned int uint16 ;typedef unsigned char uint8 ;/*/Port Config#define CE S3C2410_GPF3#define CE_OUTP S3C2410_GPF3_OUTP#define SCK S3C2410_GPF4#define SCK_OUTP S3C2410_GPF4_OUTP#define MISO S3C2410_GPG3#define MISO_INP S3C2410_GPG3_INP#define IRQ S3C2410_GPG0#define IR

4、Q_OUTP S3C2410_GPG0_OUTP#define MOSI S3C2410_GPG5#define MOSI_OUTP S3C2410_GPG5_OUTP#define CSN S3C2410_GPG6#define CSN_OUTP S3C2410_GPG6_OUTP*/Port Config/*#define CSN S3C2410_GPF3#define CSN_OUTP S3C2410_GPF3_OUTP#define MOSI S3C2410_GPF4#define MOSI_OUTP S3C2410_GPF4_OUTP#define IRQ S3C2410_GPG3#

5、define IRQ_INP S3C2410_GPG3_INP#define MISO S3C2410_GPG0#define MISO_INP S3C2410_GPG0_INP#define SCK S3C2410_GPG5#define SCK_OUTP S3C2410_GPG5_OUTP#define CE S3C2410_GPG6#define CE_OUTP S3C2410_GPG6_OUTP*/#define CSN S3C2410_GPF(3)#define CSN_OUTP S3C2410_GPIO_OUTPUT#define MOSI S3C2410_GPF(4)#defin

6、e MOSI_OUTP S3C2410_GPIO_OUTPUT#define IRQ S3C2410_GPG(3)#define IRQ_INP S3C2410_GPIO_OUTPUT#define MISO S3C2410_GPG(0)#define MISO_INP S3C2410_GPIO_INPUT#define SCK S3C2410_GPG(5)#define SCK_OUTP S3C2410_GPIO_OUTPUT#define CE S3C2410_GPG(6)#define CE_OUTP S3C2410_GPIO_OUTPUT#define DEVICE_NAME NRF2

7、4L01 /Device name锛宲ath:/proc/devices#define NRF24L01_MAJOR 241 /Device num#define TxBufSize 32uint8 TxBufTxBufSize= 0x01,0x02,0x03,0x4,0x05,0x06,0x07,0x08, 0x09,0x10,0x11,0x12,0x13,0x14,0x15,0x16, 0x17,0x18,0x19,0x20,0x21,0x22,0x23,0x24, 0x25,0x26,0x27,0x28,0x29,0x30,0x31,0x32,;/NRF24L01 Port#define

8、 CE_OUT s3c2410_gpio_cfgpin(CE, CE_OUTP) #define CE_UP s3c2410_gpio_pullup(CE, 1) #define CE_L s3c2410_gpio_setpin(CE, 0) #define CE_H s3c2410_gpio_setpin(CE, 1) #define SCK_OUT s3c2410_gpio_cfgpin(SCK, SCK_OUTP) #define SCK_UP s3c2410_gpio_pullup(SCK, 1) #define SCK_L s3c2410_gpio_setpin(SCK, 0) #d

9、efine SCK_H s3c2410_gpio_setpin(SCK, 1) #define MISO_IN s3c2410_gpio_cfgpin(MISO, MISO_INP)#define MISO_UP s3c2410_gpio_pullup(MISO, 1) #define MISO_STU s3c2410_gpio_getpin(MISO) #define IRQ_IN s3c2410_gpio_cfgpin(IRQ, IRQ_INP) #define IRQ_UP s3c2410_gpio_pullup(IRQ, 1) #define IRQ_L s3c2410_gpio_se

10、tpin(IRQ, 0) #define IRQ_H s3c2410_gpio_setpin(IRQ, 1) #define MOSI_OUT s3c2410_gpio_cfgpin(MOSI, MOSI_OUTP) #define MOSI_UP s3c2410_gpio_pullup(MOSI, 1) #define MOSI_L s3c2410_gpio_setpin(MOSI, 0) #define MOSI_H s3c2410_gpio_setpin(MOSI, 1) #define CSN_OUT s3c2410_gpio_cfgpin(CSN, CSN_OUTP)#define

11、CSN_UP s3c2410_gpio_pullup(CSN, 1) #define CSN_L s3c2410_gpio_setpin(CSN, 0) #define CSN_H s3c2410_gpio_setpin(CSN, 1) /NRF24L01#define TX_ADR_WIDTH 5 / 5 uint8s TX address width#define RX_ADR_WIDTH 5 / 5 uint8s RX address width#define TX_PLOAD_WIDTH 32 / 20 uint8s TX payload#define RX_PLOAD_WIDTH 3

12、2 / 20 uint8s TX payloaduint8 const TX_ADDRESSTX_ADR_WIDTH= 0x34,0x43,0x10,0x10,0x01; /send addruint8 const RX_ADDRESSRX_ADR_WIDTH= 0x34,0x43,0x10,0x10,0x01; /recv addr/NRF24L01 Register#define READ_REG 0x00 / 璇诲瘎瀛樺櫒鎸囦护#define WRITE_REG 0x20 / 鍐欏瘎瀛樺櫒鎸囦护#define RD_RX_PLOAD 0x61 / 璇诲彇鎺敹鏁版嵁鎸囦护#define W

13、R_TX_PLOAD 0xA0 / 鍐欏緟鍙戞暟鎹 寚浠?#define FLUSH_TX 0xE1 / 鍐叉礂鍙戦?FIFO鎸囦护#define FLUSH_RX 0xE2 / 鍐叉礂鎺敹 FIFO鎸囦护#define REUSE_TX_PL 0xE3 / 瀹氫箟閲嶅 瑁呰浇鏁版嵁鎸囦护#define NOP 0xFF / 淇濈暀/SPI(nRF24L01)瀵勫瓨鍣湴鍧#define CONFIG 0x00 / 閰嶇疆鏀跺彂鐘舵侊紝CRC鏍獙妯紡浠強鏀跺彂鐘舵佸搷搴旀柟寮?#define EN_AA 0x01 / 鑷 姩搴旂瓟鍔熻兘璁剧疆#define EN_RXADDR 0x02 / 鍙

14、敤淇亾璁剧疆#define SETUP_AW 0x03 / 鏀跺彂鍦板潃瀹藉害璁剧疆#define SETUP_RETR 0x04 / 鑷 姩閲嶅彂鍔熻兘璁剧疆#define RF_CH 0x05 / 宸綔棰戠巼璁剧疆#define RF_SETUP 0x06 / 鍙戝皠閫熺巼銆佸姛鑰楀姛鑳借 缃?#define STATUS 0x07 / 鐘舵佸瘎瀛樺櫒#define OBSERVE_TX 0x08 / 鍙戦佺洃娴嬪姛鑳?#define CD 0x09 / 鍦板潃妫娴? #define RX_ADDR_P0 0x0A / 棰戦亾0鎺敹鏁版嵁鍦板潃#define RX_ADDR_P1 0x0B

15、 / 棰戦亾1鎺敹鏁版嵁鍦板潃#define RX_ADDR_P2 0x0C / 棰戦亾2鎺敹鏁版嵁鍦板潃#define RX_ADDR_P3 0x0D / 棰戦亾3鎺敹鏁版嵁鍦板潃#define RX_ADDR_P4 0x0E / 棰戦亾4鎺敹鏁版嵁鍦板潃#define RX_ADDR_P5 0x0F / 棰戦亾5鎺敹鏁版嵁鍦板潃#define TX_ADDR 0x10 / 鍙戦佸湴鍧瀵勫瓨鍣?#define RX_PW_P0 0x11 / 鎺敹棰戦亾0鎺敹鏁版嵁闀垮害#define RX_PW_P1 0x12 / 鎺敹棰戦亾0鎺敹鏁版嵁闀垮害#define RX_PW_P2 0x13 /

16、鎺敹棰戦亾0鎺敹鏁版嵁闀垮害#define RX_PW_P3 0x14 / 鎺敹棰戦亾0鎺敹鏁版嵁闀垮害#define RX_PW_P4 0x15 / 鎺敹棰戦亾0鎺敹鏁版嵁闀垮害#define RX_PW_P5 0x16 / 鎺敹棰戦亾0鎺敹鏁版嵁闀垮害#define FIFO_STATUS 0x17 / FIFO鏍堝叆鏍堝嚭鐘舵佸瘎瀛樺櫒璁剧疆 uint8 init_NRF24L01(void);uint8 SPI_RW(uint8 tmp);uint8 SPI_Read(uint8 reg);void SetRX_Mode(void);uint8 SPI_RW_Reg(uint8 reg

17、, uint8 value);uint8 SPI_Read_Buf(uint8 reg, uint8 *pBuf, uint8 uchars);uint8 SPI_Write_Buf(uint8 reg,const uint8 *pBuf, uint8 uchars);unsigned char nRF24L01_RxPacket(unsigned char* rx_buf);void nRF24L01_TxPacket(unsigned char * tx_buf);/鍏眬鍙橀噺uint8 opencount = 0;/uint8 sta; /Status Symbol#define RX_

18、DR 6#define TX_DS 5#define MAX_RT 4 uint8 init_NRF24L01(void)/* CE_UP; SCK_UP; MISO_UP; IRQ_UP; MOSI_UP; CSN_UP; */ MISO_UP; CE_OUT; CSN_OUT; SCK_OUT; MOSI_OUT; MISO_IN; IRQ_IN; udelay(500); CE_L; / chip enable ndelay(60); CSN_H; / Spi disable ndelay(60); SCK_L; / Spi clock line init high ndelay(60)

19、; SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); /write send addr SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, RX_ADDRESS, RX_ADR_WIDTH); /write recv addr SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); / 棰戦亾0鑷 姩 ACK搴旂瓟鍏佽 SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); / 鍏佽 鎺敹鍦板潃鍙 湁棰戦亾0锛屽 鏋滈渶瑕佸 棰戦亾鍙 互鍙傝働age21

20、 SPI_RW_Reg(WRITE_REG + RF_CH, 0); / 璁剧疆淇亾宸綔涓?.4GHZ锛屾敹鍙戝繀椤讳竴鑷? SPI_RW_Reg(WRITE_REG + RX_PW_P0, RX_PLOAD_WIDTH); /璁剧疆鎺敹鏁版嵁闀垮害锛屾湰娆缃 负32瀛楄妭 SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); /璁剧疆鍙戝皠閫熺巼涓?MHZ锛屽彂灏勫姛鐜囦负鏈澶?dB SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); / IRQ鏀跺彂瀹屾垚涓 柇鍝嶅簲锛?6浣岰RC 锛屼富鎺敹 mdelay(1000); nRF24L01_

21、TxPacket(TxBuf); SPI_RW_Reg(WRITE_REG+STATUS,0XFF); printk(test 1 n); mdelay(1000);/* nRF24L01_TxPacket(TxBuf); SPI_RW_Reg(WRITE_REG+STATUS,0XFF); printk(test 2 n); mdelay(1000); nRF24L01_TxPacket(TxBuf); SPI_RW_Reg(WRITE_REG+STATUS,0XFF); printk(test 3 n); mdelay(1000); nRF24L01_TxPacket(TxBuf); SP

22、I_RW_Reg(WRITE_REG+STATUS,0XFF); printk(test 4 n); mdelay(1000);*/ return (1);/鍑芥暟锛歶int8 SPI_RW(uint8 tmp)/鍔熻兘锛歂RF24L01鐨凷PI鍐欐椂搴弔mpuint8 SPI_RW(uint8 tmp) uint8 bit_ctr; for(bit_ctr=0 ;bit_ctr8 ;bit_ctr+) / output 8-bit if(tmp & 0x80) / output tmp, MSB to MOSI MOSI_H; else MOSI_L; tmp = 1; / shift ne

23、xt bit into MSB. SCK_H; / Set SCK high. ndelay(60); tmp |= MISO_STU; / capture current MISO bit SCK_L; / .then set SCK low again ndelay(60); return(tmp); / return read tmp /鍑芥暟锛歶int8 SPI_Read(uint8 reg)/鍔熻兘锛歂RF24L01鐨凷PI鏃跺簭uint8 SPI_Read(uint8 reg) uint8 reg_val; CSN_L; / CSN low, initialize SPI comm

24、unication. ndelay(60); SPI_RW(reg); / Select register to read from. reg_val = SPI_RW(0); / .then read registervalue CSN_H; / CSN high, terminate SPI communication ndelay(60); return(reg_val); / return register value /鍔熻兘锛歂RF24L01璇诲啓瀵勫瓨鍣嚱鏁?uint8 SPI_RW_Reg(uint8 reg, uint8 value) uint8 status; CSN_L;

25、 / CSN low, init SPI transaction ndelay(60); status = SPI_RW(reg); / select register SPI_RW(value); / .and write value to it. CSN_H; / CSN high again ndelay(60); return(status); / return nRF24L01 status uint8 /鍑芥暟锛歶int8 SPI_Read_Buf(uint8 reg, uint8 *pBuf, uint8 uchars)/鍔熻兘: 鐢簬璇绘暟鎹 紝reg锛氫负瀵勫瓨鍣湴鍧锛宲Bu

26、f锛氫负寰呰 鍑烘暟鎹 湴鍧锛寀chars锛氳 鍑烘暟鎹 殑涓 暟uint8 SPI_Read_Buf(uint8 reg, uint8 *pBuf, uint8 uchars) uint8 status,uint8_ctr; CSN_L; / Set CSN low, init SPI tranaction ndelay(60); status = SPI_RW(reg); / Select register to write to and read status uint8 for(uint8_ctr=0;uint8_ctruchars;uint8_ctr+) pBufuint8_ctr

27、= SPI_RW(0); / ndelay(20); CSN_H; ndelay(60); return(status); / return nRF24L01 status uint8/鍑芥暟锛歶int8 SPI_Write_Buf(uint8 reg, uint8 *pBuf, uint8 uchars)/鍔熻兘: 鐢簬鍐欐暟鎹 細涓哄瘎瀛樺櫒鍦板潃锛宲Buf锛氫负寰呭啓鍏暟鎹 湴鍧锛寀chars锛氬啓鍏暟鎹 殑涓 暟uint8 SPI_Write_Buf(uint8 reg,const uint8 *pBuf, uint8 uchars) uint8 status,uint8_ctr; C

28、SN_L; /SPI浣胯兘 ndelay(60); status = SPI_RW(reg); for(uint8_ctr=0; uint8_ctruchars; uint8_ctr+) / SPI_RW(*pBuf+); ndelay(20); CSN_H; /鍏抽棴SPI ndelay(60); return(status); / /鍑芥暟锛歷oid SetRX_Mode(void)/鍔熻兘锛氭暟鎹 帴鏀堕厤缃?void SetRX_Mode(void) CE_L; ndelay(60);/ SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); / IRQ鏀跺彂瀹屾垚涓 柇鍝嶅簲锛?6浣岰RC 锛屼富鎺敹 /udelay(1); CE_H; udelay(130);