FPGA实训作业程序实训报告.docx

1、FPGA实训作业程序实训报告 1、计数器的设计用VHDL语言设计一个模为60，具有异步复位、同步置数功能的计数器，并用QuartusII软件仿真。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count60 is port(clk,clr,en:in std_logic; jishu_gout:out std_logic_vector(3 downto 0); jishu_siout:out std_logic_vector(3 downto 0);end count60;arch

2、itecture behave of count60 is signal jishu1,jishu10:std_logic_vector(3 downto 0); begin process(clk,clr,en) begin if(clr=1)then jishu10); jishu100); elsif(clkevent and clk=1)then if(en=1)then jishu1=0000; jishu10=0000; else if(jishu1=1001and jishu10=0101)then jishu10=0000; jishu1=0000; elsif(jishu11

3、001)then jishu1=jishu1+1; else jishu1=0000; if(jishu100101)then jishu10=jishu10+1; else jishu10=0000; end if; end if; end if; end if; jishu_gout=jishu1; jishu_siout=jishu10; end process; end behave; 60计数器的仿真结果： 2、分频器的设计：用VHDL语言设计一个通用的可输出输入信号的2分频信号、4分频信号、8分频信号、16分频信号的分频电路，并用QuartusII软件仿真。library ieee

4、;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin is port(clk_in:in std_logic; clk2,clk4,clk8,clk16:out std_logic);end fenpin;architecture behave of fenpin is signal q: std_logic_vector(3 downto 0); begin process(clk_in) begin if(clk_inevent and clk_in=1)then q=q+1; end if;

5、end process; clk2=q(0); clk4=q(1); clk8=q(2); clk16=q(3); end;分频器的仿真结果： 3、编码器的设计：用VHDL语言设计一个8-3编码器的VHDL程序，并用QuartusII软件仿真。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity code83 is port(din:in std_logic_vector(7 downto 0); code:out std_logic_vector(2 downto 0);end code

6、83;architecture behave of code83 is begin process(din) begin if(din(7)=0)then code=000; elsif(din(6)=0)then code=001; elsif(din(5)=0)then code=010; elsif(din(4)=0)then code=011; elsif(din(3)=0)then code=100; elsif(din(2)=0)then code=101; elsif(din(1)=0)then code=110; elsif(din(0)=0)then code=111; en

7、d if; end process;end;编码器的仿真结果：4、移位寄存器的设计：用VHDL语言设计一个8位的移位寄存器，使其具有左移一位或右移一位，并行输入和同步复位的功能，并用QuartusII软件仿真。 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yuwei is port(clk,rst,shift_left,shift_right:in std_logic; data:in std_logic_vector(7 downto 0); code:in std_logic

8、_vector(1 downto 0); q:out std_logic_vector(7 downto 0) ;end yuwei;architecture behave of yuwei is begin process(clk,rst) begin if rising_edge(clk) then if(rst=1)then qqqqnull; end case; end if; end if; end process;end;移位寄存器的仿真结果：5、智力抢答器的设计：用VHDL语言设计一款可容纳四组参赛者的数字智力抢答器，要求如下：（1）每组设置一个抢答按钮供抢答者使用。（2）电路具

9、有第一抢答信号的鉴别和锁存功能。在主持人将系统复位并发出抢答指令后，若参加者按抢答开关，则该组指示灯亮并用组别显示电路显示抢答者的组别，同时扬声器发出“嘟嘟”的双音音响，且持续23秒。此时，电路应具备自锁功能，使别组的抢答开关不起作用。（3）设置计分电路。每组在开始时预置成100分，抢答后由主持人计分，答对一次加10分，否则减10分。（4）设置犯规电路。对提前抢答和超时抢答的组别鸣喇叭示警，并由组别显示电路显示出犯规组别。（5）用QuartusII软件仿真，并下载到实验箱上硬件仿真。（1）抢答器：library ieee;use ieee.std_logic_1164.all;use ieee

10、.std_logic_unsigned.all;entity qiangda is port(rst,clk,a,b,c,d:in std_logic; tmp:out std_logic; states:buffer std_logic_vector(3 downto 0);end qiangda;architecture one of qiangda is signal stat:std_logic_vector(3 downto 0); begin p1:process(a,b,c,d,rst,clk) begin if(rst=1)then stat=0000; tmp=0; elsi

11、f(clkevent and clk=1)then if(a=1or stat(0)=1)and not( stat(1)=1or stat(2)=1or stat(3)=1)then stat(0)=1; end if; if(b=1or stat(1)=1)and not( stat(0)=1or stat(2)=1or stat(3)=1)then stat(1)=1; end if; if(c=1or stat(2)=1)and not( stat(0)=1or stat(1)=1or stat(3)=1)then stat(2)=1; end if; if(d=1or stat(3)

12、=1)and not( stat(0)=1or stat(1)=1or stat(2)=1 )then stat(3)=1; end if; tmp=(a or b or c or d); end if; end process p1; p2: process(states(0),states(1),states(2),states(3) begin if(stat=0000)then states=0000; elsif(stat=0001)then states=0001; elsif(stat=0010)then states=0010; elsif(stat=0100)then sta

13、tes=0011; elsif(stat=1000)then states codes codes codes codes codes=1111110;-0 end case; end process; end;仿真结果：（3）计分器：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jifen is port(clk,rst1,add:in std_logic; chos:in std_logic_vector(3 downto 0); aa2,aa1,aa0,bb2,bb1,bb0

14、:out std_logic_vector(3 downto 0); cc2,cc1,cc0,dd2,dd1,dd0:out std_logic_vector(3 downto 0);end jifen;architecture one of jifen is begin process(clk,rst1,add,chos) variable al2:std_logic_vector(3 downto 0):=0001; variable al1:std_logic_vector(3 downto 0):=0000; variable bl2:std_logic_vector(3 downto

15、 0):=0001; variable bl1:std_logic_vector(3 downto 0):=0000; variable cl2:std_logic_vector(3 downto 0):=0001; variable cl1:std_logic_vector(3 downto 0):=0000; variable dl2:std_logic_vector(3 downto 0):=0001; variable dl1:std_logic_vector(3 downto 0):=0000; begin if(clkevent and clk=1)then if(rst1=1)t

16、hen al2:=0001; al1:=0000; bl2:=0001; bl1:=0000; cl2:=0001; cl1:=0000; dl2:=0001; dl1:=0000; elsif(chos=0001)then -a if(add=1)then if(al1=1001)then al1:=0000; al2:=al2+1; if(al2=1001)then al2:=0000; end if; else al1:=al1+1; end if; end if; elsif(chos=0010)then -b if(add=1)then if(bl1=1001)then bl1:=0

17、000; bl2:=bl2+1; if(bl2=1001)then bl2:=0000; end if; else bl1:=bl1+1; end if; end if; elsif(chos=0011)then -c if(add=1)then if(cl1=1001)then cl1:=0000; cl2:=cl2+1; if(cl2=1001)then cl2:=0000; end if; else cl1:=cl1+1; end if; end if; elsif(chos=0100)then -d if(add=1)then if(cl1=1001)then cl1:=0000; c

18、l2:=cl2+1; if(cl2=1001)then cl2:=0000; end if; else cl1:=cl1+1; end if; end if; end if; end if; aa2=al2;aa1=al1;aa0=0000; bb2=bl2;bb1=bl1;bb0=0000; cc2=cl2;cc1=cl1;cc0=0000; dd2=dl2;dd1=dl1;dd0=0000; end process;end;仿真结果：（4）鸣响：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

19、entity mingxiang is port(clk,ing:in std_logic; q:out std_logic);end mingxiang;architecture one of mingxiang is signal warm:std_logic; signal nn:integer range 0 to 10; begin q=warm; process(clk) begin if(clkevent and clk=1)then if(ing=0)then warm=0; elsif(ing=1and nn=9)then warm=not warm; nn=nn+1; el

20、se warm=0; end if; end if; end process;end; 仿真结果： （5）智力抢答器的元件例化；library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity chandaci is port(clk,rst,rst1,a,b,c,d,add:in std_logic; q:out std_logic; codes:out std_logic_vector(6 downto 0); states:out std_logic_vector(3 downto 0); aa

21、2,aa1,aa0,bb2,bb1,bb0:out std_logic_vector(3 downto 0); cc2,cc1,cc0,dd2,dd1,dd0:out std_logic_vector(3 downto 0);end chandaci;architecture behave of chandaci is signal tmp1:std_logic; signal stat:std_logic_vector(3 downto 0); component qiangda port(clk,rst,a,b,c,d:in std_logic; tmp:out std_logic; st

22、ates:out std_logic_vector(3 downto 0); end component; component code port(ain4:in std_logic_vector(3 downto 0); codes:out std_logic_vector(6 downto 0); end component; component jifen port( clk,add,rst1:in std_logic; chos:in std_logic_vector(3 downto 0); aa2,aa1,aa0,bb2,bb1,bb0:out std_logic_vector(3

23、 downto 0); cc2,cc1,cc0,dd2,dd1,dd0:out std_logic_vector(3 downto 0); end component; component mingxiang port(clk,ing:in std_logic; q:out std_logic ); end component; begin u0:qiangda port map(clk,rst,a,b,c,d,tmp1,stat); u1:code port map(stat,codes); u2:jifen port map(clk,rst1,add,stat,aa2,aa1,aa0,bb2,bb1,bb0,cc2,cc1,cc0,dd2,dd1,dd0); u3: mingxiang port map(clk,tmp1,q); end;仿真结果：