计算机组成与体系结构A卷.docx

1、计算机组成与体系结构A卷姓名 学号 学院 专业 座位号 ( 密 封 线 内 不 答 题 )密封线线_ _ 诚信应考,考试作弊将带来严重后果！ 华南理工大学期末考试 计算机组成与体系结构 试卷A注意事项：1. 考前请将密封线内填写清楚； 2. 所有答案请直接答在试卷上； 3考试形式：闭卷； 4. 本试卷共 三 大题，满分100分， 考试时间120分钟。题 号一二三四五总分得 分评卷人I. 单选题（2 points each）For each question in this section, choose 1 answer. Choose the best answer.1. Which one

2、 of these will cause overflow in signed addition? .A. If there is a carry out of the least significant bit. B. If there is a carry out of the most significant bit.C. If adding two negative numbers results in a positive result. D. If the magnitude of the result is smaller than the magnitude of the sm

3、aller added.2. A major advantage of direct mapping of cache is its simplicity. The main disadvantage of this organization is that .A. It does not allow simultaneous access to the intended data and its tag.B. Its more expensive than more other types of cache organizations.C. The cache hit ratio is de

4、graded if two or more blocks used alternately map onto the same block frame in the cache.D. Its access time is greater than that of other cache organizations. 3. In an interrupt process, the usage of saving PC is .A. to make CPU find the entry address of the interrupt service routineB. to continue f

5、rom the program breakpoint when returning from interruptC. to make CPU and peripherals working in parallelD. to enable interrupt nesting4. What is the effect of the following instruction? .move ecx, ebp+8A. Add 8 to the contents of ebp and store the sum in ecx.B. Add 8 to the contents of ebp, treat

6、the sum as a memory address and store the contents at that address in ecx.C. Add 8 to the contents of the memory location whose address is stored in ebp and store the sum in ecx.D. Add the contents of ebp to the contents of memory address 8 and store the sum in ecx.5. The part of machine level instr

7、uction, which tells the central processor what was to be Done is .A. operation code B. address C. operand D. none of the above6. In a cache memory system, for a write operation, if the cache location and the main memory location are updated simultaneously, then it uses technique.A. write-back B. wri

8、te-out C. write-allocation D. write-through7. is the process by which the next device to become the bus master is selected and bus mastership is transferred to it.A. Bus phase B. Bus arbitration C. Bus timing D. Bus transceiver8. Which one of the following about benefits of virtual memory is not tru

9、e? .A. provide large address space B. relieve programmers from burden of overlaysC. resolve internal fragmentation D. simplify relocation9. A hard disk with 5 platters has 2048 tracks/platter, 1024 sectors/track (fixed number of sectors per track), and 512 byte sectors. What is its total capacity? .

10、A. 5GB B. 10GB C. 15GB D. 20GB10. Translate the IEEE single-precision floating point numbers shown below to their decimal equivalent. .A. +832 B. -832 C. +416 D. -41611. In microprogram-controlled machines, the relationship between the machine instruction and the microinstruction is .A. a machine in

11、struction is executed by a microinstructionB. a microinstruciton is composed of several machine instructionsC. a machine instruction is interpreted by a microroutine composed of microinstructionsD. a microroutine is executed by a machine instruction12. In the following statements, is not true.A. Bra

12、nch instructions can cause delays in pipelined processors, because the processor cannot determine which instruction to fetch next until the branch has executed.B. Structural hazards occur when the processors hardware is not capable of executing all the instructions in the pipeline simultaneously.C.

13、Pipelining increases processor performance by decreasing the execution time of an instruction.D. Data hazards occur when the pipeline changes the order of read/write accesses to operands so that the order differs from the order seen by sequentially executing instructions on the unpipelined machine.1

14、3. Interrupts generated by the keyboard will interrupt the CPU .A. only when the CPU is executing a busy-loop.B. only when the CPU is not doing any useful work.C. after the CPU has turned on the interrupt-enable flag.D. when the CPU is executing time-critical work.14. In a computer with a microprogr

15、ammable control unit the period of the clock is determined by .A. the delay of the control memory.B. the delay of the main memory.C. the delay of the ALU.D. the sum of two of the above delays.15. If the 2010 version of a computer executes a program in 200s and the version of the computer made in the

16、 year 2011 executes the same program in 120s, then the speedup that the manufacturer has achieved over the two-year period is .A. 1.44 B. 1.78 C. 1.53 D. 1.67II. 简答题 (5 points each)1. What is the difference between the DMA and interrupt-driven methods？（from two ways to analyze: (1) What time should

17、CPU response DMA request or interrupt request? (2) Which work should CPU need to do when it acknowledges DMA request or interrupt request?）Solution:2. A set-associative cache consists of a total 32 blocks divided into 4-block sets. The main memory contains 1024 blocks, each consisting of 64 words.(1

18、) How many bits are there in a main memory address?(2) How many bits are there in each of the TAG, SET, and WORD fields?Solution:3. The two unsigned binary numbers shown below are to be multiplied using a multiplier that uses Booths Algorithm:1 0 0 1 1 0 1 0X 0 1 1 1 0 1 1 1(1) How many bits will be

19、 needed to store the product of these two numbers?(2) How many additions and subtractions will be performed by the Booths Algorithm multiplier respectively?Solution:4. What are the advantages and disadvantages of hardwired and microprogrammed control?Solution:III. 综合题（10 points each）1. Assume that a

20、 computers instruction length is 16-bit, and its operand address is 6-bit. Suppose the designers need two-address instructions, one-address instructions and zero-address instructions. How should we design the instruction format? And specify the numbers of each type of instruction can be designed.Sol

21、ution:2. Consider that floating-point numbers are represented in a 12-bit format. The scale factor has an implied base of 2 and a 5-bit, excess-15 exponent, with the two end value of 0 and 31 used to signify exact 0 and infinity, respectively. The 6-bit mantissa is normalized as in the IEEE format,

22、with an implied 1 to the left of the binary point.(1) Represent the numbers -0.6875 and +19 in this format.(2) Perform Sub Operation on the operands A = 0 10001 011011, B = 1 01111 101010. ( Note: Using rounding as the truncation method in the answers. Write the computation process! )Solution: 3. A

23、logic circuit is needed to implement the priority network shown like figure below. The network handles three interrupt request lines. When a request is received on line INTRi, the network generates an acknowledgement on line INTAi. If more than one request is received, only the highest-priority requ

24、est is acknowledged, where the ordering of priority is: priority of INTR1 priority of INTR2 priority of INTR3.(1) Give a truth table for each of the outputs INTA1, INTA2, and INTA3.(2) Give logic expressions of INTA1, INTA2, INTA3 and a logic circuit for implementing this priority network.Solution:4

25、. The following figure gives part of the microinstruction sequence corresponding to one of the machine instructions of a microprogrammed computer. Microinstruction B is followed by C, D, F, or I, depending on bits IR6, IR5 and IR4 of the machine instruction register. Give the possible implementation

26、. Microinstruction sequencing is accomplished by means of a microprogram counter. Branching is achieved by microinstructions of the form: Branch to X, OR Where X is a base branch address. The branch address is modified by bit-ORing of bits IR4, IR5 and IR6 with the appropriate bits with X.Solution:5

27、. Consider the following piece of code:int i;int A1024*1024;int x=0;for (i=0;i1024;i+) x+=Ai+A1024*i;Suppose that it is executed on a system with a 2-way set associative 16KB data cache with 32-byte blocks, 32-bit words, and an LRU replacement policy. Assume that int is word-sized. Also assume that the address of a is 0x0, that i and x are in registers, and that the cache is initially empty. How many data cache misses are there? How many hits are there?Solution: