MAXVSchematicReviewWorksheet.docx

1、MAXVSchematicReviewWorksheetMAX V Device Schematic Review WorksheetThis document is intended to help you review your schematic and compare the pin usage against the MAX V Device Family Pin Connection Guidelines (PDF) version 1.0 and other referenced literature for this device family. The technical c

2、ontent is divided into focus areas such as FPGA power supplies, programming, and dual purpose I/O pins. Within each focus area, there is a table that contains the voltage or pin name for all of the dedicated and dual purpose pins for the device family. In some cases, the device density and package c

3、ombination may not include some of the pins shown in this worksheet, you should cross reference with the pin-out file for your specific device. Links to the device pin-out files are provided at the top of each section.Before you begin using this worksheet to review your schematic and commit to board

4、 layout, Altera highly recommends:1) Review the Knowledge Database for MAX V Device Known Issues and other MAX V Device Knowledge Base records. 2) Compile your design in the Quartus II software to completion. For example, there are I/O related VCCIO requirements for the I/O standards used in the dev

5、ice. If you do not have a complete project, then at a minimum a top level project should be used with all I/O pins defined, placed, and apply all of the programmable options that you plan to use. The I/O Analysis tool in the Pin Planner can then be used on the minimal project to validate the pinout

6、in the Quartus II software to assure there are no conflicts with the device rules and guidelines.When using the I/O Analysis tool you must ensure there are no errors with your pinout. Additionally, you should check all warning and critical warning messages to evaluate their impact on your design. Yo

7、u can right click your mouse over any error, warning or critical warning message and select “Help”. This will bring open a new Help window with further information on the cause of the error or warning, and the action that is required.For example, you can use electromigration current assignments to s

8、pecify the DC current draw on I/O pins that drive resistive loads, such as pull up resistors or LEDs. The device has DC current density restrictions that must be met based on the pin locations used in the design. The following error is generated if the device current density restrictions are violate

9、d:Error (169007): Current density too high in I/O bank - pins combined exceed the limit (. mA) by . mAThe help file provides the following:CAUSE:You made pin assignments in the specified range of pads, but some of the pins are too close together. The specified I/O bank draws a current that exceeds t

10、he maximum by the specified amount. The device can drive only a limited amount of current to each I/O bank. Click the + icon to display details about the specific pins, type, location, and I/O standards used in the specified I/O bank.ACTION:Reassign some pins to reduce the current density or assign

11、some pins to use an I/O standard with a lower current. To display I/O banks, open the Chip Planner and turn on I/O bank display in the Layers Settings dialog box.There are many reports available for use after a successful compilation or I/O analysis. For example, you can use the “All Package Pins” a

12、nd “I/O Bank Usage” reports within the Compilation Fitter Resource Section to see all of the I/O standards and I/O programmable options that are assigned to all of the pins in your design, as well as view the required VCCIO for each I/O bank. These reports must match your schematic pin connections.T

13、he review table has the following heading:Plane/SignalSchematic NameConnection GuidelinesComments / IssuesThe first column (Plane/Signal) lists the device voltage or signal pin name. You should only edit this column to remove dedicated or dual purpose pin names that are not available for your device

14、 density and package option.The second column (Schematic Name) is for you to enter your schematic name(s) for the signal(s) or plane connected to the device pin(s).The third column (Connection Guidelines) should be considered “read only” as this contains Alteras recommended connection guidelines for

15、 the voltage plane or signal. The fourth column (Comments/Issues) is an area provided as a “notepad” for you to comment on any deviations from the connection guidelines, and to verify guidelines are met. In many cases there are notes that provide further information and detail that compliment the co

16、nnection guidelines.Here is an example of how the worksheet can be used:Plane/SignalSchematic NameConnection GuidelinesComments / IssuesVCCINT+1.8VConnected to +1.8V plane, no isolation is necessary. Missing low and medium range decoupling, check PDN.See Notes (1-1) (1-2).Legal Note: PLEASE REVIEW T

17、HE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE USING THIS SCHEMATIC REVIEW WORKSHEET (“WORKSHEET”) PROVIDED TO YOU. BY USING THIS WORKSHEET, YOU INDICATE YOUR ACCEPTANCE OF SUCH TERMS AND CONDITIONS, WHICH CONSTITUTE THE LICENSE AGREEMENT (AGREEMENT) BETWEEN YOU AND ALTERA CORPORATION OR ITS APP

18、LICABLE SUBSIDIARIES (ALTERA).1. Subject to the terms and conditions of this Agreement, Altera grants to you, for no additional fee, a non-exclusive and non-transferable right to use this Worksheet for the sole purpose of verifying the validity of the pin connections of an Altera programmable logic

19、device-based design. You may not use this Worksheet for any other purpose. There are no implied licenses granted under this Agreement, and all rights, except for those granted under this Agreement, remain with Altera.2. Altera does not guarantee or imply the reliability, or serviceability, of this W

20、orksheet or other items provided as part of this Worksheet. This Worksheet is provided AS IS. ALTERA DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. ALTERA HAS NO OBLIGATION TO PROVIDE YOU WITH

21、 ANY SUPPORT OR MAINTENANCE.3. In no event shall the aggregate liability of Altera relating to this Agreement or the subject matter hereof under any legal theory (whether in tort, contract, or otherwise), exceed One Hundred USDollars (US$100.00). In no event shall Altera be liable for any lost reven

22、ue, lost profits, or other consequential, indirect, or special damages caused by your use of this Worksheet even if advised of the possibility of such damages.4. This Agreement may be terminated by either party for any reason at any time upon 30-days prior written notice. This Agreement shall be gov

23、erned by the laws of the State of California, without regard to conflict of law or choice of law principles. You agree to submit to the exclusive jurisdiction of the courts in the County of Santa Clara, State of California for the resolution of any dispute or claim arising out of or relating to this

24、 Agreement. The parties hereby agree that the party who is not the substantially prevailing party with respect to a dispute, claim, or controversy relating to this Agreement shall pay the costs actually incurred by the substantially prevailing party in relation to such dispute, claim, or controversy

25、, including attorneys fees. Failure to enforce any term or condition of this Agreement shall not be deemed a waiver of the right to later enforce such term or condition or any other term or condition of the Agreement. BY USING THIS WORKSHEET, YOU ACKNOWLEDGE THAT YOU HAVE READ THIS AGREEMENT, UNDERS

26、TAND IT, AND AGREE TO BE BOUND BY ITS TERMS AND CONDITIONS. YOU AND ALTERA FURTHER AGREE THAT IT IS THE COMPLETE AND EXCLUSIVE STATEMENT OF THE AGREEMENT BETWEEN YOU AND ALTERA, WHICH SUPERSEDES ANY PROPOSAL OR PRIOR AGREEMENT, ORAL OR WRITTEN, AND ANY OTHER COMMUNICATIONS BETWEEN YOU AND ALTERA REL

27、ATING TO THE SUBJECT MATTER OF THIS AGREEMENT.IndexSection I: Power Section II: ProgrammingSection III: I/OSection IV: Document Revision History Section I: Power Literature: MAX V DevicesMAX V Device Pin Out FilesMAX V Device Family Pin Connection Guidelines (PDF)Power Supply Integrity Support Page

28、(General decoupling guidelines)Power Delivery Network (PDN) Tool Power Delivery Network (PDN) Tool User Guide (PDF)Early Power EstimatorPowerPlay Power Analyzer Support ResourcesAltera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)IndexPlane/Si

29、gnalSchematic NameConnection Guidelines Comments / IssuesVCCINT All VCCINT pins require a 1.8V supply.Decoupling for these pins depends on the design decoupling requirements of the specific board.Verify Guidelines have been met or list required actions for compliance. See Notes (1-1) (1-2).VCCIO1.4

30、Supported voltages are 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.Note VCCIO1 does not support 1.2VDecoupling for these pins depends on the design decoupling requirements of the specific board.Verify Guidelines have been met or list required actions for compliance. See Notes (1-1) (1-2).Index Top of SectionPl

31、ane/SignalSchematic NameConnection Guidelines Comments / IssuesGNDGround pins for the I/O banks and internal supply. All GND pins must be connected to the board GND plane.GND pins in the 5M1270Z and 5M2210Z devices consist of GNDIO and GNDINT pins.Verify Guidelines have been met or list required actions for compliance. See Notes (1-1) (1-2).Notes:1-1. This worksheet does not calculate required decoupling, it is expected the designer will select decoupling based on analysis of power required