单片机外文翻译3.docx

1、单片机外文翻译3外文及翻译英文资料:STC89C51（8-bit Micro controller with 4K Bytes Flash）The STC89C51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible wi

2、th the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89C51 is a po

3、werful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.Features：Compatible with MCS.-51 Products4K Bytes of In-System Programmable (ISP) Flash MemoryEndurance: 1000 Write/Erase Cycles4.0V to 5.5V Operating RangeFully Static Operation

4、: 0 Hz to 33 MHzThree-level Program Memory Lock128 x 8-bit Internal RAM32 Programmable I/O LinesTwo 16-bit Timer/CountersSix Interrupt SourcesFull Duplex UART Serial ChannelLow-power Idle and Power-down ModesInterrupt Recovery from Power-down ModeWatchdog TimerDual Data PointerPower-off FlagFast Pro

5、gramming TimeFlexible ISP Programming (Byte and Page Mode)Green (Pb/Halide-free) Packaging OptionThe STC89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt a

6、rchitecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the STC89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, s

7、erial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.VCC：Supply voltage (all packages except 42-PDIP).GND：Ground (all packages except 42-

8、PDIP; for 42-PDIP GND connects only the logic core and the embedded program memory).VDD：Supply voltage for the 42-PDIP which connects only the logic core and the embedded program memory.PWRVDD：Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board MUST connect

9、both VDD and PWRVDD to the board supply voltage.PWRGND：Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the common silicon substrate, but not through any metal link. The application board MUST connect both GND and PWRGND to the board ground.

10、Port 0：Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to ext

11、ernal program and data memory. In this mode, PO has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bi-directional I/O port wit

12、h internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (lip) because of the internal p

13、ull-ups.Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being p

14、ulled low will source current (lip) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVXDPTR). In this application, Port 2 uses strong internal pull-ups when

15、emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVXRI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bi-direc

16、tional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lip) becaus

17、e of the pull-ups.Port 3 receives some control signals for Flash programming and verification.Port 3 also serves the functions of various special features of the STC89C51，as shown in the following table.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets

18、 the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROG：Address Latch Enable (ALE) is an output pulse for

19、 latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, h

20、owever, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable b

21、it has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external program memory.When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipp

22、ed during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on

23、reset.EA should be strapped to Vcc for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillat

24、or amplifierSpecial Function Registers：Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not writ

25、e 1 s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Interrupt Registers:The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the

26、five interrupt sources in the IP register.Dual Data Pointer Registers:To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DPO at SFR address locations 82H-83H and DP1 at 84H-85H.Bit DPS=0 in SFR AUXR1 selects DPO and DPS=1 selects

27、DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to 1”during power up. It can be set and rest under software control and

28、is not affected by reset.Memory Organization：MCS-51 devices have a separate address space for Program and Data Memory. Up to 64Kbytes each of external Program and Data Memory can be addressed.Program Memory：If the EA pin is connected to GND, all program fetches are directed to external memory. On th

29、e STC89S51，if EA is connected to Vcc, program fetches to addresses OOOOH through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.Data Memory：The STC89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and

30、 indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.Watchdog Timer (One-time Enabled with Reset-out)：The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The W

31、DT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01 EH and OE1 H in sequence to the WDTRST register (SFR location OA6H). When the WDT is enabled, it will increment every machine cycle w

32、hile the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.Timer 0 and 1：Timer 0 and Timer 1 is a 16-bit Timer/Counter.中文翻译:STC89C51 (8位微控制单片机，片内含4K bytes可系统编程的存储器)STC89C51是美国ATMEL公司生产的低功耗，高性能CMOS 8位单片机，片内含4k bytes的可系统编程的Flash只读程序存储器，器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准8051指令系统及引脚。它集Flash程序存储器既可在线编程（ISP)