数字逻辑电路实验报告.docx

1、数字逻辑电路实验报告数字逻辑电路实验报告实验二：16进制译码器原理图：GAL方程：PLD16V8BASIC GATES2009.04.16LQY USTC V0.1W X Y Z NC NC NC NC NC GNDNC A B C D E F G NC VCC/A=/W*/X*/Y*Z+/W*X*/Y*/Z+W*/X*Y*Z+W*X*/Y*Z/B=/W*/X*/Y*Z+/W*X*/Y*Z+/W*X*Y*/Z+W*/X*Y*Z+W*X*/Y*/Z+W*X*Y*/Z/C=/W*/X*/Y*Z+/W*/X*Y*/Z+W*X*/Y*/Z+W*X*Y*/Z+W*X*Y*Z/D=/W*/X*/Y*Z+/

2、W*X*/Y*/Z+/W*X*Y*Z+W*/X*Y*/Z+W*X*Y*Z/E=/W*/X*Y*Z+/W*X*/Y*/Z+/W*X*/Y*Z+/W*X*Y*Z+W*/X*/Y*Z/F=/W*/X*Y*/Z+/W*/X*Y*Z+/W*X*Y*Z+W*X*/Y*Z/G=/W*/X*/Y*Z+/W*X*Y*Z+W*X*/Y*/Z+/W*/X*/Y*/ZDESCRIPTION注释：实验中使用的是共阳极数码管，设计的时候还没有化简VHDL代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY code16 IS PORT(w,x,y,z: IN STD_LOG

3、IC; A,b,c,d,e,f,g:OUT STD_LOGIC );END code16;ARCHITECTURE WORK OF code16 IS BEGINA=(NOT W AND NOT X AND NOT Y AND Z) OR (NOT W AND X AND NOT Y AND NOT Z) OR (W AND NOT X AND Y AND Z) OR (W AND X AND NOT Y AND NOT Z);B=(NOT W AND NOT X AND NOT Y AND Z) OR (NOT W AND X AND NOT Y AND Z) OR (NOT W AND X

4、 AND Y AND NOT Z) OR (W AND NOT X AND Y AND Z) OR (W AND X AND NOT Y AND NOT Z) OR (W AND X AND Y AND NOT Z);C=(NOT W AND NOT X AND NOT Y AND Z) OR (NOT W AND NOT X AND Y AND NOT Z) OR (W AND X AND NOT Y AND NOT Z) OR (W AND X AND Y AND NOT Z) OR (W AND X AND Y AND Z);D=(NOT W AND NOT X AND NOT Y AN

5、D Z) OR (NOT W AND X AND NOT Y AND NOT Z) OR (NOT W AND X AND Y AND Z) OR (W AND NOT X AND Y AND NOT Z) OR (W AND X AND Y AND Z);E=(NOT W AND NOT X AND Y AND Z) OR (NOT W AND X AND NOT Y AND NOT Z) OR (NOT W AND X AND NOT Y AND Z) OR (NOT W AND X AND Y AND Z) OR (W AND NOT X AND NOT Y AND Z);F=(NOT

6、W AND NOT X AND Y AND NOT Z) OR (NOT W AND NOT X AND Y AND Z) OR (NOT W AND X AND Y AND Z) OR (W AND X AND NOT Y AND Z);NOT G=(NOT W AND NOT X AND NOT Y AND Z) OR (NOT W AND X AND Y AND Z) OR (W AND X AND NOT Y AND NOT Z) OR (NOT W AND NOT X AND NOT Y AND NOT Z);END WORK;实验三：海明校验电路原理图：做实验时，造错在总线上造错，

7、导致读和写没有很好体现出来。GAL方程：PLD01V0HAMMING2009.04.16LQY USTC V0.1A B C D EA EB EC ED NC GNDNC S1 S2 S3 R1 R2 R3 R4 NC VCCIA=A $ EAIB=B $ EBIC=C $ ECID=D $ EDK1=A $ B $ DK2=A $ C $ DK3=B $ C $DS1=A $ B $ D $ K1S2=A $ C $ D $ K2S3=B $ C $ D $ K3E1=S1*S2*S3E2= S1*S2*/S3E3= S1*/S2*/S3E4=/S1*S2*S3R1=A $ E1R2=B $

8、 E2R3=C $ E3R4=D $ E4DESCRIPTIONVHDL代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY hamm ISPORT(i1,i2,i3,i4,e1,e2,e3,e4:IN STD_LOGIC; r1,r2,r3,k1,k2,k3,k4:OUT STD_LOGIC);END hamm;ARCHITECTURE hamming OF hamm IS SIGNAL s1,s2,s3,b1,b2,b3,b4,c1,c2,c3,c4,d1,d2,d3,d4:STD_LOGIC;BEGINb1=i1 XOR e1;b2=i2

9、XOR e2;b3=i3 XOR e3;b4=i4 XOR e4;s1=i4 XOR i2 XOR i1;s2=i4 XOR i3 XOR i1;s3=i4 XOR i3 XOR i2;c1=b4 XOR b2 XOR b1 XOR s1;c2=b4 XOR b3 XOR b1 XOR s2;c3=b4 XOR b3 XOR b2 XOR s3;d1=c1 AND c2 AND (NOT c3) AND (NOT c4);d2=c1 AND (NOT c2) AND (NOT c3) AND c4;d3=(NOT c1) AND c2 AND c3 AND c4;d4=c1 AND c2 AN

10、D c3 AND c4;r1=c1;r2=c2;r3=c3;k1=d1 XOR c1;k2=d2 XOR c2;k3=d3 XOR c3;k4=d4 XOR c4;END hamming;实验四：时序脉冲分频电路原理图：二分频电路四分频电路五分频电路三周期电路GAL方程：VHDL代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY exp5tx IS PORT(clk : IN STD_LOGIC; CP1,CP2,CP3,CP4,CP5,CP6 : OUT STD_LOGIC; Q3,Q4,Q4b,Q5,Q6,Q7,Q8 : BUFFER ST

11、D_LOGIC);END exp5tx;ARCHITECTURE DISTRIBUTER OF exp5tx ISBEGIN PROCESS(clk,Q3,Q5) VARIABLE count_5 : STD_LOGIC_VECTOR(2 DOWNTO 0); VARIABLE count_2 : STD_LOGIC; VARIABLE count_4 : STD_LOGIC_VECTOR(1 DOWNTO 0); VARIABLE count_3 : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN IF(clkEVENT AND clk=1)THEN IF(count

12、_5=000)THEN count_5 = 001;Q3 = 1; ELSIF(count_5=001)THEN count_5 := 010;Q3 = 0; ELSIF(count_5=010)THEN count_5 := 011;Q3 = 0; ELSIF(count_5=011)THEN count_5 := 100;Q3 = 0; ELSIF(count_5=100)THEN count_5 := 000;Q3 = 0; END IF; END IF; IF(Q3EVENT AND Q3=1)THEN IF(count_2=0)THEN count_2 := 1; Q4 = 1;Q4

13、b = 0; ELSIF(count_2=1)THEN count_2 := 0; Q4 = 0;Q4b = 1; END IF; END IF; IF(Q3EVENT AND Q3=1)THEN IF(count_4=00)THEN count_4 := 01;Q5 = 1; ELSIF(count_4=01)THEN count_4 := 10;Q5 = 1; ELSIF(count_4=10)THEN count_4 := 11;Q5 = 0; ELSIF(count_4=11)THEN count_4 := 00;Q5 = 0; END IF; END IF; IF(Q5EVENT A

14、ND Q5=1)THEN IF(count_3=00)THEN count_3 := 01; Q6 = 1;Q7 = 0;Q8 = 0; ELSIF(count_3=01)THEN count_3 := 10; Q6 = 0;Q7 = 1;Q8 = 0; ELSIF(count_3=10)THEN count_3 := 00; Q6 = 0;Q7 = 0;Q8 = 1; END IF; END IF; END PROCESS; CP1 = Q4b AND Q5 AND Q6; CP2 = Q4b AND NOT Q5 AND Q6; CP3 = Q4b AND Q5 AND Q7; CP4 =

15、 Q4b AND NOT Q5 AND Q7; CP5 = Q4b AND Q5 AND Q8; CP6 = Q4b AND NOT Q5 AND Q8;END DISTRIBUTER;实验五：串并转换电路原理图：控制逻辑十六进制计数器GAL方程：VHDL代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY sp IS PORT(clk,rd: IN STD_LOGIC; s7,s6,s5,s4,s3,s2,s1,s0:OUT STD_LOGIC );END sp;ARCHITECTURE WORK OF sp IS SIGNAL clr,ccl

16、k,c2,c16,d7,d6,d5,d4,d3,d2,d1,d0,st: STD_LOGIC;BEGIN PROCESS(clk) VARIABLE count_4 : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN IF(clkEVENT AND clk=1)THEN IF(count_4=00)THEN count_4 := 01;c2 = 1; ELSIF(count_4=01)THEN count_4 := 11;c2 = 0; ELSIF(count_4=11)THEN count_4 := 10;c2 = 0; ELSIF(count_4=10)THEN c

17、ount_4 := 00;c2 = 0; END IF; END IF; END PROCESS; PROCESS(c2,rd) VARIABLE count_2 : STD_LOGIC; BEGIN IF(c2EVENT AND c2=1)THEN d0=rd; d1=d0; d2=d1; d3=d2; d4=d3; d5=d4; d6=d5; d7=d6; END IF; END PROCESS; PROCESS(clk,d7,d6,d5,d4,d3,d2,d1,d0) BEGIN IF(clkEVENT AND clk=1)THEN IF(d7=0 and d6=1 and d5=1 a

18、nd d4=1 and d3=1 and d2=1 and d1=1 and d0=0)THEN st = 0; ELSIF(d7=1 and d6=0 and d5=0 and d4=0 and d3=0 and d2=0 and d1=0 and d0=1)THEN st = 1; END IF; END IF; cclk = st AND clk; IF(d7=0 and d6=1 and d5=1 and d4=1 and d3=1 and d2=1 and d1=1 and d0=0)THEN clr=1; ELSIF(d7=1 and d6=0 and d5=0 and d4=0

19、and d3=0 and d2=0 and d1=0 and d0=1)THEN clr=1; ELSE clr=0; END IF; END PROCESS; PROCESS VARIABLE count_4 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN WAIT ON cclk UNTIL (cclkEVENT AND cclk=1); IF(count_4=0000)THEN count_4 := 0001;c16 = 0; ELSIF(count_4=0001)THEN count_4 := 0010;c16 = 0; ELSIF(count_4=0010

20、)THEN count_4 := 0011;c16 = 0; ELSIF(count_4=0011)THEN count_4 := 0100;c16 = 0; ELSIF(count_4=0100)THEN count_4 := 0101;c16 = 0; ELSIF(count_4=0101)THEN count_4 := 0110;c16 = 0; ELSIF(count_4=0110)THEN count_4 := 0111;c16 = 0; ELSIF(count_4=0111)THEN count_4 := 1000;c16 = 0; ELSIF(count_4=1000)THEN

21、count_4 := 1001;c16 = 0; ELSIF(count_4=1001)THEN count_4 := 1010;c16 = 0; ELSIF(count_4=1010)THEN count_4 := 1011;c16 = 0; ELSIF(count_4=1011)THEN count_4 := 1100;c16 = 0; ELSIF(count_4=1100)THEN count_4 := 1101;c16 = 0; ELSIF(count_4=1101)THEN count_4 := 1110;c16 = 0; ELSIF(count_4=1110)THEN count_4 := 1111;c16 = 0; ELSIF(count_4=1111)THEN count_4 := 0000;c16 = 1; END IF; END PROCESS; PROCESS(c16,st,clr) BEGIN IF(c16 =0 OR st=0 OR clr=1)THEN s0=Z; s1=Z; s2=Z; s3=Z; s4=Z; s5=Z; s6=Z; s7=Z; ELSE s0=d0; s1=d1; s2=d2; s3=d3; s4=d4; s5=d5; s6=d6; s7=d7; END IF; END PROCESS; END WORK;