EDA课程设计UART控制器设计.docx

1、EDA课程设计UART控制器设计波特率发生模块VHDL描述library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity baud is port( clk:in std_logic; resetb:in std_logic; baud_set:in std_logic_vector(7 downto 0); baud_set_wr:in std_logic; bclk:out std_logic);end baud;architecture

2、 behav of baud is signal baud_count:std_logic_vector(7 downto 0); signal cnt:std_logic_vector(7 downto 0);beginprocess(clk) begin if clkevent and clk=1 then if (resetb=1) then cnt=00000001; bclk=0; elsif (baud_set_wr=1) then baud_count=baud_set; cnt=00000001; elsif (cnt=baud_count) then cnt=00000001

3、; bclk=1; else cnt=cnt+1; bclk=0; end if; end if;end process;end behav;UART发送模块VHDL描述library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity UART_Transfer is Port ( bclkt:in std_logic; resett:in std_logic; cmd_p:in std_logic; txdbuf:in std_logic_v

4、ector(7 downto 0); txd:out std_logic; txd_done:out std_logic);end UART_Transfer;architecture behav of UART_Transfer is type states is (s_idle,s_start,s_wait,s_shift,s_stop); signal state: states:=s_idle; signal tcnt: integer:=0; signal xcnt16: std_logic_vector(4 downto 0):=00000; signal prob: std_lo

5、gic_vector(4 downto 0);beginprocess(bclkt) variable xbitcnt:integer:=0; variable framlent:integer:=8; variable txds:std_logic; begin if(bclktevent and bclkt=1) then if(resett=1) then state=s_idle; txd_done if (cmd_p=1) then state=s_start; txd_done=0; else state=s_idle; txd_done if (xcnt16=01111) the

6、n txds:=0; state=s_wait; xcnt16=00000; else xcnt16=xcnt16+1; state if(xcnt16=01110) then if (xbitcnt=framlent) then state=s_stop; xbitcnt:=0; else state=s_shift; end if; xcnt16=00000; else xcnt16=xcnt16+1; state txds:=txdbuf(xbitcnt); xbitcnt:=xbitcnt+1; state if (xcnt16=01111) then if (cmd_p=0) the

7、n state=s_idle; xcnt16=00000; else xcnt16=xcnt16; state=s_stop; end if; txd_done=1; else xcnt16=xcnt16+1; txds:=1; statestate=s_idle; end case; end if; txd=txds; prob=xcnt16; end if;end process;end behav;UART接收模块VHDL描述library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std

8、_logic_unsigned.all;entity UART_Reciever isgeneric (framlenr:integer:=8); port( bclkr:in std_logic; resetr:in std_logic; rxdr:in std_logic; s_ready:out std_logic; rbuf:out std_logic_vector(7 downto 0);end UART_Reciever;architecture behav of UART_Reciever is type states is (s_start,s_center,s_wait,s_

9、sample,s_stop); signal state: states:=s_start; signal rxd_sync: std_logic;begin pro1:process(rxdr) begin if (rxdr=0) then rxd_sync=0; else rxd_sync=1; end if; end process; pro2:process(bclkr) variable count:std_logic_vector(3 downto 0); variable rcnt:integer:=0; variable rbufs: std_logic_vector(7 do

10、wnto 0); begin if (bclkrevent and bclkr=1) then if (resetr=1) then state if (rxd_sync=0) then state=s_center; s_ready=0; rcnt:=0; else state=s_start; s_ready if (rxd_sync=0) then if (count=1000) then state=s_wait; count:=0000; else count:=count+1; state=s_center; end if; else state if (count=1110) t

11、hen if (rcnt=framlenr) then state=s_stop; else state=s_sample; end if; count:=0000; else count:=count+1; state rbufs(rcnt):=rxd_sync; rcnt:=rcnt+1; state s_ready=1; rbuf=rbufs; state state=s_start; end case; end if;end if;end process;end behav;UART顶层模块VHDL描述library ieee;use ieee.std_logic_1164.all;u

12、se ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity top isport( clk:in std_logic; reset:in std_logic; rxd:in std_logic; xmit_cmd_p_in:in std_logic; baud_set_wr:in std_logic; rec_ready:out std_logic; txd_out:out std_logic; txd_done_out:out std_logic; baud_set:in std_logic_vector(7 down

13、to 0); txdbuf_in:in std_logic_vector(7 downto 0); rec_buf:out std_logic_vector(7 downto 0);end top;architecture behav of top iscomponent UART_Receiver port( bclkr:in std_logic; resetr:in std_logic; rxdr:in std_logic; r_ready:out std_logic; rbuf:out std_logic_vector(7 downto 0);end component;component UART_Transfer Port ( bclkt:in std_logic; resett:in std_logic; xmit_cmd_p:i