梁祝程序.docx

1、梁祝程序梁祝 电子琴程序LIBRARY IEEE; - 硬件演奏电路顶层设计USE IEEE.STD_LOGIC_1164.ALL;ENTITY Songer ISPORT ( CLK12MHZ : IN STD_LOGIC; -音调频率信号 CLK8HZ : IN STD_LOGIC; -节拍频率信号 CODE1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);- 简谱码输出显示 HIGH1 : OUT STD_LOGIC; -高8度指示 SPKOUT : OUT STD_LOGIC );-声音输出END;ARCHITECTURE one OF Songer IS C

2、OMPONENT NoteTabs PORT ( clk : IN STD_LOGIC; ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END COMPONENT; COMPONENT ToneTaba PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; CODE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ; HIGH : OUT STD_LOGIC; Tone : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) ); END COMPONEN

3、T; COMPONENT Speakera PORT ( clk : IN STD_LOGIC; Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT STD_LOGIC ); END COMPONENT; SIGNAL Tone : STD_LOGIC_VECTOR (10 DOWNTO 0); SIGNAL ToneIndex : STD_LOGIC_VECTOR (3 DOWNTO 0);BEGINu1 : NoteTabs PORT MAP (clk=CLK8HZ, ToneIndex=ToneIndex);u2 : ToneTaba

4、 PORT MAP (Index=ToneIndex,Tone=Tone,CODE=CODE1,HIGH=HIGH1);u3 : Speakera PORT MAP(clk=CLK12MHZ,Tone=Tone, SpkS=SPKOUT );END;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY NoteTabs ISPORT ( clk : IN STD_LOGIC; ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );END;ARCHI

5、TECTURE one OF NoteTabs ISCOMPONENT MUSIC -音符数据ROMPORT(address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);END COMPONENT; SIGNAL Counter : STD_LOGIC_VECTOR (7 DOWNTO 0);BEGIN CNT8 : PROCESS(clk, Counter) BEGIN IF Counter=138 THEN Counter = 00000

6、000; ELSIF (clkEVENT AND clk = 1) THEN Counter Counter , q=ToneIndex, inclock=clk);END;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY Speakera ISPORT ( clk : IN STD_LOGIC; Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT STD_LOGIC );END Speakera;ARCHITECTURE one

7、OF Speakera IS SIGNAL PreCLK, FullSpkS : STD_LOGIC;BEGINDivideCLK : PROCESS(clk) VARIABLE Count4 : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PreCLK 11 THEN PreCLK = 1; Count4 := 0000; ELSIF clkEVENT AND clk = 1 THEN Count4 := Count4 + 1; END IF; END PROCESS; GenSpkS : PROCESS(PreCLK, Tone)- 11位可预置计数器 VA

8、RIABLE Count11 : STD_LOGIC_VECTOR (10 DOWNTO 0);BEGIN IF PreCLKEVENT AND PreCLK = 1 THEN IF Count11 = 16#7FF# THEN Count11 := Tone ; FullSpkS = 1; ELSE Count11 := Count11 + 1; FullSpkS = 0; END IF; END IF; END PROCESS;DelaySpkS : PROCESS(FullSpkS)-将输出再2分频，展宽脉冲，使扬声器有足够功率发音 VARIABLE Count2 : STD_LOGIC

9、;BEGIN IF FullSpkSEVENT AND FullSpkS = 1 THEN Count2 := NOT Count2; IF Count2 = 1 THEN SpkS = 1; ELSE SpkS Tone=11111111111 ; CODE=0000; HIGH Tone=01100000101 ; CODE=0001; HIGH Tone=01110010000 ; CODE=0010; HIGH Tone=10000001100 ; CODE=0011; HIGH Tone=10010101101 ; CODE=0101; HIGH Tone=10100001010 ;

10、 CODE=0110; HIGH Tone=10101011100 ; CODE=0111; HIGH Tone=10110000010 ; CODE=0001; HIGH Tone=10111001000 ; CODE=0010; HIGH Tone=11000000110 ; CODE=0011; HIGH Tone=11001010110 ; CODE=0101; HIGH Tone=11010000100 ; CODE=0110; HIGH Tone=11011000000 ; CODE=0001; HIGH NULL; END CASE; END PROCESS;END;- Copy

11、right (C) 1991-2006 Altera Corporation- Your use of Altera Corporations design tools, logic functions- and other software and tools, and its AMPP partner logic- functions, and any output files any of the foregoing- (including device programming or simulation files), and any- associated documentation

12、 or information are expressly subject- to the terms and conditions of the Altera Program License- Subscription Agreement, Altera MegaCore Function License- Agreement, or other applicable license agreement, including,- without limitation, that your use is for the sole purpose of- programming logic de

13、vices manufactured by Altera and sold by- Altera or its authorized distributors. Please refer to the- applicable agreement for further details.- Quartus II generated Memory Initialization File (.mif)WIDTH=4;DEPTH=256;ADDRESS_RADIX=UNS;DATA_RADIX=UNS;CONTENT BEGIN00: 3;01: 3;02: 3;03: 3;04: 5;05: 5;0

14、6: 5;07: 6;08: 8;09: 8;10: 8 ;11: 9 ;12: 6 ;13: 8;14: 5;15: 5;16: 12;17: 12;18: 12;19:15;20:13 ;21:12 ;22:10 ;23:12;24: 9;25: 9;26: 9;27: 9;28: 9;29: 9;30: 9 ;31: 0 ;32: 9 ;33: 9;34: 9;35:10;36: 7;37: 7;38: 6;39: 6;40: 5 ;41: 5 ;42: 5 ;43: 6;44: 8;45: 8;46: 9;47: 9;48: 3;49: 3;50: 8 ;51: 8 ;52: 6 ;5

15、3: 5;54: 6;55: 8;56: 5;57: 5;58: 5;59: 5;60: 5 ;61: 5 ;62: 5 ;63: 5;64:10;65:10;66:10;67:12;68: 7;69: 7;70: 9 ;71: 9 ;72: 6 ;73: 8;74: 5;75: 5;76: 5;77: 5;78: 5;79: 5;80: 3 ;81: 5 ;82: 3 ;83: 3;84: 5;85: 6;86: 7;87: 9;88: 6;89: 6;90: 6 ;91: 6 ;92: 6 ;93: 6;94: 5;95: 6;96: 8;97: 8;98: 8;99: 9;100:12

16、;101:12 ;102:12 ;103:10;104: 9;105: 9;106:10;107: 9;108: 8;109: 8;110: 6 ;111: 5 ;112: 3 ;113: 3;114: 3;115: 3;116: 8;117: 8;118: 8;119: 8;120: 6 ;121: 8 ;122: 6 ;123: 5;124: 3;125: 5;126: 6;127: 8;128: 5;129: 5;130: 5 ;131: 5 ;132: 5 ;133: 5;134: 5;135: 5;136: 0;137: 0;138: 0;END;Tone源程序-TONELIBRAR

17、Y IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY TONE IS -引导TONE 的子模块实体部分PORT(INDEX:IN STD_LOGIC_VECTOR(7 DOWNTO 0); -键盘输入 CODE:OUT INTEGER RANGE 0 TO 15;-输出对应的输入音阶简谱的显示数码 HIGH:OUT STD_LOGIC; TONE:OUT INTEGER RANGE 0 TO 16#7FF#); END;ARCHITECTURE ONE OF TONE ISBEGIN -BEGIN以下直到END为该模块的功能描述语句SENRCH: PROCESS(

18、INDEX)BEGIN CASE INDEX IS -译码电路，查表方式，控制音调的预置数 WHEN 00000001=TONE=773;CODE=1;HIGHTONE=912;CODE=2;HIGHTONE=1036;CODE=3;HIGHTONE=1116;CODE=4;HIGHTONE=1197;CODE=5;HIGHTONE=1290;CODE=6;HIGHTONE=1372;CODE=7;HIGHTONE=1410;CODE=1;HIGHTONE=2047;CODE=0;HIGH=0; END CASE;END PROCESS; -进程语句结束END;Speaker源程序-SPEAK

19、ERLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SPEAKER ISPORT(CLK1:IN STD_LOGIC; - 输入时钟脉冲 TONE1:IN INTEGER RANGE 0 TO 16#7FF#; SPKS:OUT STD_LOGIC);END;ARCHITECTURE ONE OF SPEAKER ISSIGNAL PRECLK,FULLSPKS:STD_LOGIC;BEGINDIVIDECLK:PROCESS(CLK1)VARIABLE COUNT4:INTEGER RANGE 0 TO 15;BEGIN PRECLK11 TH

20、EN -开始IF语句 PRECLK=1; COUNT4:=0; ELSIF CLK1EVENT AND CLK1=1 THEN COUNT4:=COUNT4+1; END IF; -IF语句结束END PROCESS;GENSPKS:PROCESS(PRECLK,TONE1) -11位可预置计数器VARIABLE COUNT11:INTEGER RANGE 0 TO 16#7FF#;BEGIN IF PRECLKEVENT AND PRECLK=1 THEN IF COUNT11=16#7FF# THEN COUNT11:=TONE1; FULLSPKS=1; ELSE COUNT11:=CO

21、UNT11+1; FULLSPKS=0; END IF; -IF语句结束 END IF;END PROCESS;DELAYSPKS:PROCESS(FULLSPKS) -将输出再二分频，展宽脉冲，使扬声器有足够的功率发音VARIABLE COUNT2:STD_LOGIC;BEGIN IF FULLSPKSEVENT AND FULLSPKS=1 THEN COUNT2:=NOT COUNT2; IF COUNT2=1 THEN SPKS=1; ELSE SPKS=0; END IF; END IF; END PROCESS; -由PROCESS引导的进程语句结束 END;Top源程序-TOPL

22、IBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY TOP ISPORT(CLK12MHZ:IN STD_LOGIC; -音调频率信号 INDEX1:IN STD_LOGIC_VECTOR(7 DOWNTO 0); -简谱码输出显示 CODE1:OUT INTEGER RANGE 0 TO 15; HIGH1,SPKOUT:OUT STD_LOGIC); -声音输出 END; ARCHITECTURE ONE OF TOP IS COMPONENT TONE PORT(INDEX:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CODE:OUT INTEGER RANGE 0 TO 15; HIGH:OUT STD_LOGIC; TONE:OUT INTEGER RANGE 0 TO 16#7FF#