数字系统设计与PLD应用 实验报告Word下载.docx

1、IN STD_LOGIC）;END TRAFFIC_CONTROL;ARCHITECTURE A OF TRAFFIC_CONTROL IS TYPE STATE_SPACE IS （S0,S1,S2,S3）;SIGNAL STATE :STATE_SPACE;BEGIN PROCESS （RESET,CLK） BEGIN IF RESET=1THEN STATE IF W1= STATE IF W2=S2; WHEN S2= IF W3=THEN=S3; END IF ; WHEN S3= END CASE ; END PROCESS; C1= WHEN STATE=S0 ELSE 0; C

2、2 WHEN STATE=S1 OR STATE=S3 ELSE C3 WHEN STATE=S2 ELSE R1 WHEN STATE=S1 OR STATE=S0 ELSE Y1 WHEN STATE=S3 ELSE G1 R2 WHEN STATE=S2 OR STATE=S3 ELSE Y2 WHEN STATE=S1 ELSE G2END A;ENTITY COUNT30 ISPORT（CLK:ENABLE :C:OUT STD_LOGIC）;END COUNT30;ARCHITECTURE A OF COUNT30 IS PROCESS（CLK） VARIABLE CNT:INTE

3、GER RANGE 30 DOWNTO 0; IF（CLK）THEN IF ENABLE=AND CNT30 THEN CNT:=CNT+1; ELSE=0; IF CNT=30 THEN C ELSE END A ;ENTITY COUNT05 IS（CLK: ENABLE: C:OUT STD_LOGIC）;END COUNT05;ARCHITECTURE A OF COUNT05 IS BEGIN INTEGER RANGE 5 DOWNTO 0;5 THEN IF CNT=5 THENENTITY COUNT26 ISEND COUNT26;ARCHITECTURE A OF COUN

4、T26 IS INTEGER RANGE 26 DOWNTO 0;26 THEN IF CNT=26 THEN实验三、九九乘法表系统的设计试设计一个供儿童学习九九乘法表之用的数字系统，该系统既可引导学习着跟随学习机连续背诵；也可随时查找任何在两个1位十进制数的相乘结果。 九九乘法表系统能够自动或手动进行两个1位十进制数的乘法，并自动显示被乘数、乘数和乘积，该系统示意图如图6-18所示。图中AA和BB分别为被乘数和乘数的外部输入端，它们用1位BCD码表示。系统用十进制七段数字显示器显示被乘数A、乘数B和乘积M的值，其中M用2位十进制显示器显示。PACKAGE PLUS_LIB IS COMPON

5、ENT PLUSCONTROL PORT（CLK: START,ARH,TT,EE: DONE,CRT,S,ENT: END COMPONENT; COMPONENT COUNT8 CRT,ENT: TT: COMPONENT CNT1 CRT: OC: QA:OUT INTEGER RANGE 9 TO 0）; COMPONENT CNT2 EN2: EE: QB: COMPONENT MUX1 PORT（BB,QB:IN INTEGER RANGE 9 DOWNTO 0; S: B:OUT INTEGER RANGE 9 DOWNTO 0）; COMPONENT MUX2 PORT（AA,

6、QA: A: COMPONENT PLUS PORT（A: M:OUT INTEGER RANGE 81 DOWNTO 0）; COMPONENT TRANS PORT（M:IN INTEGER RANGE 81 TO 0; BD2,BD1: COMPONENT DISPLAY PORT（BD1:IN INTEGER RANGE 9 TO 0; XA1:OUT STD_LOGIC_VECTOR（6 DOWNTO 0）;END PLUS_LIB;USE WORK.PLUS_LIB.ALL;ENTITY PLUSTOP IS START,ARH: BB,AA: XA1,XA2:OUT STD_LO

7、GIC_VECTOR（6 DOWNTO 0）; XA3,XA4: END PLUSTOP; ARCHITECTURE ONE OF PLUSTOP IS SIGNAL TT,EE,ENT,CRT,DONE,OC,S:STD_LOGIC; SIGNAL QA,QB,B,A:INTEGER RANGE 9 DOWNTO 0; SIGNAL M:INTEGER RANGE 81 DOWNTO 0; SIGNAL BD1,BD2: CONTROL:PLUSCONTROL PORT MAP（CLK,START,ARH,TT,EE,DONE,CRT,S,ENT）; COUNT1:COUNT8 PORT M

8、AP（CLK,CRT,ENT,TT）; COUNT2:CNT1 PORT MAP（CLK,CRT,OC,QA）; COUNT3:CNT2 PORT MAP（CLK,CRT,OC,EE,QB）; M1:MUX1 PORT MAP（BB,QB,S,B）; M2:MUX2 PORT MAP（AA,QA,S,A）; P1:PLUS PORT MAP（A,B,M）; T1:TRANS PORT MAP（M,BD2,BD1）; X1:DISPLAY PORT MAP（A,XA1）; X2: PORT MAP（B,XA2）; X3: PORT MAP（BD1,XA3）; X4: PORT MAP（BD2,X

9、A4）; END ONE;ENTITY PLUSCONTROL IS PORT（ CLK:END PLUSCONTROL;ARCHITECTURE ONE OF PLUSCONTROL IS TYPE STATE_SPACE IS（S0,S1,S2,S3）; SIGNAL STATE: CASE STATE IS IF START= IF ARH= IF TT= IF EE= END CASE; DONE WHEN STATE=S0 ELSE CRT S WHEN STATE=S3 ELSE ENT WHEN STATE=S2 ELSEEND ONE;ENTITY COUNT8 ISPORT（

10、CLK : IN STD_LOGIC; TT:END;ARCHITECTURE ONE OF COUNT8 IS VARIABLE COUNT:INTEGER RANGE 0 TO 7; IF CLK THEN IF CRT= AND ENT= IF COUNT=7 THEN COUNT: TT ELSE=COUNT+1; END IF; END IF; END IF;ENTITY CNT1 IS OC:OUT INTEGER RANGE 0 TO 9）;ARCHITECTURE ONE OF CNT1 ISINTEGER RANGE 0 TO 9; IF CLK IF CRT= IF COU

11、NT=9 THEN COUNT: OC ELSIF COUNT=8 THEN ELSE QA=COUNT;ENTITY CNT2 IS CRT : EN2 : EE : QB :ARCHITECTURE ONE OF CNT2 IS IF EN2= IF COUNT=9 THEN EE ELSE EE QBENTITY TRANS ISPORT（M:IN INTEGER RANGE 0 TO 81;END TRANS;ARCHITECTURE ONE OF TRANS IS PROCESS（M）IF M=9 THENBD2BD1=M;ElSIF M=19 THEN=1;=M-10;=29 TH

12、EN=2;=M-20;=39 THEN=3;=M-30;=49 THEN=4;=M-40;=59 THEN=5;=M-50;=69 THEN=6;=M-60;=79 THEN=7;=M-70;ElSE=8;=M-80;END IF;END PROCESS;ENTITY DISPLAY ISEND DISPLAY;ARCHITECTURE ONE OF DISPLAY IS WITH（BD1） SELECT XA1=0000001 WHEN 0, 1001111 WHEN 1,0010010 WHEN 2,0000110 WHEN 3,1001100 WHEN 4,0100100 WHEN 5,

13、0100000 WHEN 6,0001111 WHEN 7,0000000 WHEN 8,0000100 WHEN 9; LIBRARY IEEE;ENTITY MUX1 ISPORT（BB,QB:IN INTEGER RANGE 0 TO 9;S:B:OUT INTEGER RANGE 0 TO 9END MUX1;ARCHITECTURE ONE OF MUX1 IS B=QB WHEN S=ELSE BB;ENTITY MUX2 ISPORT（AA,QA:A:END MUX2;ARCHITECTURE ONE OF MUX2 IS A=QA WHEN S=ELSE AA;ENTITY PLUS ISPORT（A:M:OUT INTEGER RANGE 0 TO 81）;END PLUS;ARCHITECTURE ONE OF PLUS IS M=A*B;