SSI接口Word格式文档下载.docx

1、发送电路和接收电路相互独立，但是共用串行时钟和帧同步时钟。SSI模块引脚信号描述SSICLKIN：SSI时钟输入信号。SSI_BCLK：SSI串行比特时钟。SSI_MCLK：SSI串行主时钟信号，在SSI主模式下，该信号也作为过采样时钟信号。SSI_FS：SSI串行帧同步信号。SSL_RXD：SSI串行接收数据信号。SSI_TXD：SSI串行发送数据信号。SSI的操作模式SSI有3种基本同步操作模式：普通模式、网络模式和门时钟模式。普通模式是最简单的模式，一帧内只能传输一个字，而且每一帧都需要帧同步信号来控制同步；网络模式主要用于多时隙的情况下，一帧内可以传输2个字到32个字不等；门时钟SSI

2、_BCLK模式下，串行比特时钟SSI_BCLK指示了发送引脚或接收引脚上的有效数据，所以不需要帧同步信号。除了上述3种基本模式外，针对音频上的应用，SSI还支持两种衍生模式I2S模式和AC97模式，分别用于传输I2S和AC97音频格式数据。SSI的初始化初始化SSI模块的正确顺序：上电或重启SSI（SSI_CRSSI_EN=0），即关闭SSI模块功能。配置SSI模块。涉及的寄存器包括控制寄存器SSI_CR、中断允许寄存器SSI_IER、发送配置寄存器SSI_TCR、接收配置寄存器SSI_RCR和时钟控制寄存器SSI_CCR。通过SSI_IER寄存器设置必要的中断或DMA。设置SSI_CRSSI

3、_EN=1允许SSI模块功能。设置SSI_CRTERE，开始发送接收数据。SSI的工作过程（1）发送数据单通道时，数据从串行发送数据寄存器SSI_TX0中传到发送移位寄存器TXSR中，再通过串行发送引脚SSI_TXD发送出去，然后根据用户设置情况决定是否产生发送中断。如果发送缓冲区TXFIFOO被允许，则SSI_TX0继续从TXFIFOO中取数据，直到TXFIFOO中的数据全部被发送，再通过用户设置情况决定是否产生发送中断。双通道时，发送移位寄存器TXSR交替从SSI_TX0和SSI_TXl中取出数据。（2）接收数据单通道时，数据从串行接收引脚SSI_RXD进来，由接收移位寄存器RXSR传输给

4、接收数据寄存器SSI_RX0，再根据用户设置情况决定是否产生接收中断。如果接收缓冲区RXFIFOO被允许，则SSI_RX0将数据写入RXFIFOO，并继续从接收移位寄存器中获取数据。双通道时，接收移位寄存器RXSR交替将数据传输给SSI_RX0和SSI_RXl。Synchronous Serial Interface （SSI） is a widely used serial interface standard for industrial applications between a master （e.g. controller） and a slave （e.g. sensor）. S

5、SI is based on RS4221 standards and has a high protocol efficiency in addition to its implementation over various hardware platforms, making it very popular among sensor manufacturers. SSI was originally developed by Max Stegmann GMBH in 1984 for transmitting the position data of absolute encoders -

6、 for this reason, some servo/drive equipment manufacturers refer to their SSI port as a Stegmann Interface. It was formerly covered by the German patent DE 34 45 617 which expired in 1990. It is very suitable for applications demanding reliability and robustness in measurements under varying industr

7、ial environments.IntroductionSSI is a synchronous, point to point, serial communication channel for digital data transmission.Synchronous data transmission is one in which, the data is transmitted by synchronizing the transmission at the receiving and sending ends using a common clock signal. Since

8、start and stop bits are not present, this allows the use of transmission bandwidth for more message bits and makes the whole transmission process simpler and easier. Figure 1 - SSI Point to Point CommunicationIn general, as mentioned earlier it is a point to point connection from a master （e.g. PLC,

9、 Microcontroller） to a slave （e.g. Rotary encoders）. The master controls the clock sequence and the slave transmits the current data/value through a shift register. When invoked by the master, the data is clocked out from the shift register. The master and slave are synchronized by the common clock

10、of the controller.The CLOCK and DATA signals are transmitted according to RS-422 standards. RS-422, also known as ANSI/TIA/EIA-422-B, is a technical standard that specifies the electrical characteristics of the balanced voltage digital interface circuit. Data is transmitted using balanced or differe

11、ntial signalling i.e. the CLOCK and DATA lines are basically twisted pair cables.Inputs can use an opto-coupler for galvanic isolation （For more details see 1） that can be driven by RS-422/485 levels. The DATA output of the sensor is driven by a RS-422/485 line driver. Differential signalling improv

12、es the resistance to electromagnetic interference （EMI）, hence making it a reliable communication channel over long transmission lengths and harsh external environments. SSI DesignThe interface has a very simple design as illustrated in the above figure. It consists of 2 pairs of wires, one for tran

13、smitting the clock signals from the master and the other for transmitting the data from the slave. The clock sequences are triggered by the master when need arises. Different clock frequencies can be used ranging from 100 kHz to 2 MHz and the number of clock pulses depends on the number of data bits

14、 to be transmitted.The simplest SSI slave interface uses a retriggerable monostable multivibrator （monoflop） to freeze the current value of the sensor. The current frozen values of the slave are stored in Shift registers. These values are clocked out sequentially when initiated by the controller. Th

15、e design is being revolutionized with the integration of microcontrollers, FPGAs and ASICs into the interface.The data format is designed in such a way to ensure proper communication of data. The protocol for the data transmission is based on three different subsequent parts （Leading-”1 - Data-Bits

16、- Trailing-0）. The main significance of this type of format is to ensure the proper working of the interface and hence secure data transmission free from any hardware or software errors.In idle state the CLOCK is on high level and also the sensor output is on high level, so that it can be used for d

17、etecting any broken wire contacts. This helps in observing the proper working condition of the interface.After n-CLOCK pulses （rising edges） the data is completely transmitted. With the next CLOCK pulse （rising edge n+1） the sensor output goes to low level which can be used to detect a short circuit

18、 in the cable. If it is high even after n+1 rising edges then it means that the interface has a short circuit.Readings from multiple slaves（up to 3） can be enabled at the same time by connecting them to a common clock. However, to avoid ground loops and electrically isolate the slave, complete galva

19、nic isolation by opto-couplers is needed.SSI Timing and TransmissionThe following keywords will be useful in understanding the SSI data transmission procedure.tm represents the transfer timeout （Monoflop time）. It is the minimum time required by the slave to realise that the data transmission is com

20、plete. After tm, the data line goes to idle and the slave starts updating its data in the shift register.tp represents the pause time. It is the time delay between two consecutive clock sequences from the master.tw represents the repetition time. It is the minimum time elapsed between retransmission

21、s of the same data and is always less than tm.T represents the width of each clock cycle. It is the time taken between two falling or two rising edges in a continuous clock sequence.MSB: Most significant bitLSB: Least significant bitSingle TransmissionSingle Transmission of the SSI Interface: 1. Fre

22、ezing of the data. 2. Transmission of the first Databit. 3. End of transmission. 4. after the pause time the SSI went back to idle state - is ready for new transmission.The diagram illustrates the single data transmission using SSI protocol:The SSI is initially in the idle mode, where both the data

23、and clock lines stay HIGH and the slave keeps updating its current data.The transmission mode is evoked when the master initiates a train of clock pulses. Once the slave receives the beginning of the clock signal （1）, it automatically freezes its current data. With the first rising edge （2） of the c

24、lock sequence, the MSB of the sensors value is transmitted and with consequent rising edges, the bits are sequentially transmitted to the output.After the transmission of complete data word （3） （i.e. LSB is transmitted）, an additional rising edge of the clock sets the clock line HIGH. The data line

25、is set to LOW and remains there for a period of time, tm, to recognize the transfer timeout . If a clock signal （data-output request） is received within that time, the same data will be transmitted again （multiple transmission）.The slave starts updating its value and the data line is set to HIGH （id

26、le mode） if there are no clock pulses within time, tm. This marks the end of single transmission of the data word. Once the slave receives a clock signal at a time, tp （=tm）, the updated position value is frozen and the transmission of the value begins as described earlier.Multiple TransmissionsMult

27、iple transmissionMultiple transmissions of the same data happens only if there is continuous clocking even after the transmission of the least significant bit i.e. the clock pulses does not allow the monoflop to go to steady state. This is illustrated below.The initial sequences are the same as that

28、 of the single transmission. In the idle state the CLOCK and DATA lines are high but with the arrival of the first falling edge the transmission mode is evoked and the similarly the data bits are transmitted sequentially starting with the MSB with every rising edge. The transmission of the LSB means

29、 that the transmission of the data is completed. An additional rising edge pushes the data line to LOW signifying the end of transmission of the particular data.But, if there are continuous clock pulses even after then （ i.e. the next clock pulses comes in time tw （ tm ） the value of the slave is no

30、t updated. This is because the monoflop is still unsteady and the value in the shift register still contains the same value as before. So with the next rising edge, i.e. after the n+1 rising edge, the transmission of the same data continues and the MSB of data transmitted earlier is re-transmitted a

31、t the end of tw.Then, it follows the same procedure as earlier transmissions, leading to multiple transmissions of the same data. The value of the slave is updated only when the timing between two clock pulses is more than the transfer timeout, tm.Multiple transmission is used to check the data integrity. The two consecutive received values are compared, transmission failures are indicated by differences between the two values.Interrupting TransmissionThe transmission of data is controlled by the master and the transmission can be interrupted at any t