现代CMOS工艺基本流程.ppt

1、现代现代CMOS工艺工艺基本流程基本流程现代CMOS工艺基本流程1Silicon Substrate P+2um725umSilicon Epi Layer P选择衬底晶圆的选择掺杂类型（N或P）电阻率（掺杂浓度）晶向高掺杂(P+)的Si晶圆低掺杂(P)的Si外延层2Silicon Substrate P+Silicon Epi Layer P Pad Oxide热氧化热氧化形成一个SiO2薄层，厚度约20nm高温，H2O或O2气氛缓解后续步骤形成的Si3N4对Si衬底造成的应力3Silicon Substrate P+Silicon Epi Layer P-Silicon NitrideSi

2、3N4淀积Si3N4淀积厚度约250nm化学气相淀积(CVD)作为后续CMP的停止层4Silicon Substrate P+Silicon Epi Layer P-Silicon NitridePhotoresist光刻胶成形光刻胶成形厚度约0.51.0um光刻胶涂敷、曝光和显影用于隔离浅槽的定义5Silicon Substrate P+Silicon Epi Layer P-Silicon NitridePhotoresistSi3N4和SiO2刻蚀Si3N4和SiO2刻蚀基于氟的反应离子刻蚀(RIE)6Silicon Substrate P+Silicon Epi Layer P-Sil

3、icon NitridePhotoresistTransistor Active AreasIsolation Trenches隔离浅槽刻蚀隔离浅槽刻蚀基于氟的反应离子刻蚀(RIE)定义晶体管有源区7Silicon Substrate P+Silicon Epi Layer P-Silicon NitrideTransistor Active AreasIsolation Trenches除去光刻胶除去光刻胶氧等离子体去胶，把光刻胶成分氧化为气体8Silicon Substrate P+Silicon Epi Layer P-Silicon NitrideFuture PMOS Transis

4、torSilicon DioxideFuture NMOS TransistorNo current can flow through here!SiO2淀积SiO2淀积用氧化物填充隔离浅槽厚度约为0.51.0um，和浅槽深度和几何形状有关化学气相淀积(CVD)9Silicon Substrate P+Silicon Epi Layer P-Silicon NitrideFuture PMOS TransistorFuture NMOS TransistorNo current can flow through here!化学机械抛光化学机械抛光(CMP)CMP除去表面的氧化层到Si3N4层为

5、止10Silicon Substrate P+Silicon Epi Layer P-Future PMOS TransistorFuture NMOS Transistor除去Si3N4除去Si3N4热磷酸(H3PO4)湿法刻蚀，约18011Trench OxideCross SectionBare Silicon平面视图完成浅槽隔离(STI)12Silicon Substrate P+Silicon Epi Layer P-Future PMOS TransistorFuture NMOS TransistorPhotoresist光刻胶成形光刻胶成形厚度比较厚，用于阻挡离子注入用于N-阱

6、的定义13Silicon Substrate P+Silicon Epi Layer P-Future NMOS TransistorPhotoresistN-WellPhosphorous(-)Ions磷离子注入磷离子注入高能磷离子注入形成局部N型区域，用于制造PMOS管14Silicon Substrate P+Silicon Epi Layer P-Future NMOS TransistorN-Well除去光刻胶15PhotoresistSilicon Substrate P+Silicon Epi Layer P-Future NMOS TransistorN-Well光刻胶成形光刻

7、胶成形厚度比较厚，用于阻挡离子注入用于P-阱的定义16Silicon Substrate P+Silicon Epi Layer P-PhotoresistN-WellBoron(+)IonsP-Well硼离子注入高能硼离子注入形成局部P型区域，用于制造NMOS管硼离子注入17Silicon Substrate P+Silicon Epi Layer P-N-WellP-Well除去光刻胶18Silicon Substrate P+Silicon Epi Layer P-P-WellN-Well退火退火在6001000的H2环境中加热修复离子注入造成的Si表面晶体损伤注入杂质的电激活同时会造成

8、杂质的进一步扩散快速加热工艺(RTP)可以减少杂质的扩散19Trench OxideN-WellP-WellCross Section完成N-阱和P-阱平面视图20Silicon Substrate P+Silicon Epi Layer P-P-WellN-Well Sacrificial Oxide牺牲氧化层生长牺牲氧化层生长牺牲氧化层生长厚度约25nm用来捕获Si表面的缺陷21Silicon Substrate P+Silicon Epi Layer P-P-WellN-Well除去牺牲氧化层除去牺牲氧化层HF溶液湿法刻蚀剩下洁净的Si表面22Silicon Substrate P+Si

9、licon Epi Layer P-P-WellN-Well Gate Oxide栅氧化层生长栅氧化层生长工艺中最关键的一步厚度210nm要求非常洁净，厚度精确(1)用作晶体管的栅绝缘层23Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPolysilicon多晶硅淀积多晶硅淀积厚度150300nm化学气相淀积(CVD)24Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresistChannel LengthPolysilicon光刻胶成形光刻胶成形工艺中最关键的图形转移

10、步骤栅长的精确性是晶体管开关速度的首要决定因素使用最先进的曝光技术深紫外光(DUV)光刻胶厚度比其他步骤薄25Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresistChannel Length多晶硅刻蚀多晶硅刻蚀基于氟的反应离子刻蚀(RIE)必须精确的从光刻胶得到多晶硅的形状26Silicon Substrate P+Silicon Epi Layer P-P-WellN-Well Gate Oxide Poly Gate Electrode除去光刻胶27Trench OxideN-WellP-WellCross Sect

11、ionPolysilicon平面视图完成栅极28Silicon Substrate P+Silicon Epi Layer P-P-WellN-Well Gate Oxide Poly Gate Electrode Poly Re-oxidation多晶硅氧化多晶硅氧化在多晶硅表面生长薄氧化层用于缓冲隔离多晶硅和后续步骤形成的Si3N429Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresist光刻胶成形光刻胶成形用于控制NMOS管的衔接注入30Silicon Substrate P+Silicon Epi Layer P-

12、P-WellN-WellPhotoresistArsenic(-)IonsN TipNMOS管衔接注入NMOS管衔接注入低能量、浅深度、低掺杂的砷离子注入衔接注入用于削弱栅区的热载流子效应31Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN Tip除去光刻胶32Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresistN Tip光刻胶成形光刻胶成形用于控制PMOS管的衔接注入33Silicon Substrate P+Silicon Epi Layer P-P-Well

13、N-WellPhotoresistBF2(+)IonsN TipP TipPMOS管衔接注入低能量、浅深度、低掺杂的BF2+离子注入衔接注入用于削弱栅区的热载流子效应PMOS管衔接注入34Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN TipP Tip除去光刻胶35Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellSilicon NitrideThinner HereThicker HereN TipP TipP TipSi3N4淀积Si3N4淀积厚度120180nmCVD36Si

14、licon Substrate P+Silicon Epi Layer P-P-WellN-WellSpacer SidewallN TipP TipP TipSi3N4刻蚀Si3N4刻蚀水平表面的薄层Si3N4被刻蚀，留下隔离侧墙侧墙精确定位晶体管源区和漏区的离子注入RIE37Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresistN TipP Tip光刻胶成形光刻胶成形用于控制NMOS管的源/漏区注入38Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotore

15、sistArsenic(-)IonsN+DrainN+SourceP TipNMOS管源/漏注入NMOS管源/漏注入浅深度、重掺杂的砷离子注入，形成了重掺杂的源/漏区隔离侧墙阻挡了栅区附近的注入39Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP Tip除去光刻胶40Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourcePhotoresistP Tip光刻胶成形光刻胶成形用于控制PMOS管的源/漏区注入41Silicon Sub

16、strate P+Silicon Epi Layer P-P-WellN-WellBF2(+)IonsPhotoresistN+DrainN+SourceP+SourceP+DrainPMOS管源/漏注入PMOS管源/漏注入浅深度、重掺杂的BF2+离子注入，形成了重掺杂的源/漏区隔离侧墙阻挡了栅区附近的注入42Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+SourceP+DrainLightly Doped“Tips”除去光刻胶和退火除去光刻胶和退火用RTP工艺，消除杂质在源/漏区的迁移43Trench OxidePolysiliconCross SectionN-WellP-WellN+Source/DrainP+Source/DrainSpacer平面视图完成晶体管源/漏极，电子器件形成44Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+Source除去表面氧化物除去表面氧化物在HF溶液中