计算机原理与接口技术Word文件下载.docx

1、（predictable, though not necessarily fast） response to events in the embedded system they are controlling. When certain events occur, aninterruptsystem can signal the processor to suspend processing the current instruction sequence and to begin aninterrupt service routine（ISR, or interrupt handler）.

2、 The ISR will perform any processing required based on the source of the interrupt, before returning to the original instruction sequence. Possible interrupt sources are device dependent, and often include events such as an internal timer overflow, completing an analog to digital conversion, a logic

3、 level change on an input such as from a button being pressed, and data received on a communication link. Where power consumption is important as in battery operated devices, interrupts may also wake a microcontroller from a low power sleep state where the processor is halted until required to do so

4、mething by a peripheral event.MCS 8051The 8051 architecture provides many functions （CPU,RAM,ROM,I/O,logic,timer, etc.） in a singlepackage 8-bitALUandAccumulator, 8-bitRegisters（one16-bitregister with specialmove instructions）, 8-bitdata busand 2x16-bitaddress bus/program counter/data pointerand rel

5、ated 8/11/16-bit operations; hence it is mainly an8-bitmicrocontroller Booleanprocessor with 17 instructions, 1-bit accumulator, 32 registers （4 bit addressable 8-bit） and up to 144 special 1-bit addressable RAM variables （18 bit addressable 8-bit）3 Multiply, divide andcompareinstructions 4 fastswit

6、chable register bankswith 8 registers each （memory mapped） Fast interrupt with optional register bank switching Interruptsthreadswith selectable priority4 Dual 16-bitaddress bus It can access 2 x 216memory locations 64kB（65536 locations） each of RAM and ROM 128bytesof on-chip RAM （IRAM） 4KiBof on-ch

7、ip ROM, with a 16-bit （64 KiB） address space （PMEM）. Not included on 803X variants Four 8-bitbi-directionalport UART （serial port） Two 16-bit Counter/timers Power savingmode （on some derivatives）The only register on an 8051 that is not memory-mapped is the 16-bit program counter PC. This specifies t

8、he address of the next instruction to execute. Relative branch instructions supply an 8-bit signed offset which is added to the PC.The following registers are memory-mapped into the special function register space: （0x81） Stack pointer SP. This is an 8-bit register used by subroutine call and return

9、 instructions. The stack grows upward; the SP is incremented before pushing, and decremented after popping a value. （0x8283） Data pointer DP. This is a 16-bit register that is used for accessing PMEM and XRAM. （0xD0） Program status word PSW. This contains important status flags: PSW.0: P Parity. Giv

10、es the parity （modulo-2 sum of the bits of） the most recent ALU result. PSW.1: UD User Defined. For general software use, not otherwise used by hardware. PSW.2: OVOverflow flag. Set when addition produces a signed overflow. PSW.3: RS0 Register select 0. The low-order bit of the register bank. Set wh

11、en banks at 0x08 or 0x18 are in use. PSW.4: RS1 Register select 1. The high-order bit of the register bank. Set when banks at 0x10 or 0x18 are in use. PSW.5: F0 Flag 0. For general software use, not otherwise used by hardware. PSW.6: ACauxiliary carry. Set when addition produces a carry from bit 3 t

12、o bit 4. PSW.7: CCarry bit. （0xE0） Accumulator A. This register is used by most instructions. （0xF0） B register. This is used as an extension to the accumulator for multiply and divide instructions.In addition, there are 8 general purpose registers R0R7, mapped to IRAM between 0x00 and 0x1F. Only 8

13、bytes of that range are used at any given time, determined by the bank select bits in the PSW.256 single bits are directly addressable. These are the 16 IRAM locations from 0x200x2F, and the 16 special function registers 0x80, 0x88, 0x90, , 0xF8.Note that the PSW does not contain the common N （negat

14、ive） and Z （zero） flags. Instead, because the accumulator is a bit-addressible SFR, it is possible to branch on individual bits of it, including the msbit. There is also an instruction to jump if the accumulator is zero or non-zero.Instructions are all 1 to 3 bytes long, consisting of an initial opc

15、ode byte, followed by up to 2 bytes of operands.There are 16 basic ALU instructions that operate between the accumulator and a second operand, specified using one of the following addressing modes: Register direct, R0R7 （opcodesx8xF） Register indirect, R0 or R1 （opcodesx6 andx7） Memory direct, speci

16、fying an IRAM or SFR location （opcodesx5, followed by 1 byte of address） Immediate, specifying an 8-bit constant （opcodesx4, followed by 1 byte of data）The instructions are as follows. Not all support all addressing modes; the immediate mode in particular is sometimes nonsensical: 0yINCoperand: Incr

17、ement the specified operand. Opcode 04 specifies INC A 1yDEC Decrement the specified operand. Opcode 14 specifies DEC A 2yADD A,operand: Add the operand to the accumulator A. 3yADDC A,operand: Add the operand, plus the C bit, to the accumulator. 4yORL A,operand: Logical OR the operand into the A reg

18、ister. 5yANL A,operand: Logical AND the operand into the A register. 6yXRL A,operand: Logical exclusive-OR the operand into the A register. 7yMOVoperand,#data: Move immediate data to the operand. Opcode 74 specifies MOV A,#data. 8yaddress,operand: Move data to an IRAM or SFR register. 9ySUBB A,opera

19、nd: Subtract the operand from the accumulator, with borrow. Note there is no subtractwithoutborrow. Ayoperand,address: Move data from an IRAM or SFR register. Opcodes A4 and A5 are not used. ByCJNEoperand,#data,offset: Compareoperandto the immediatedata, and branch to PC+addressif not equal. Opcodes

20、 B4 and B5 perform CJNE A,operand,offset, for memory direct and immediate operands. Note there is no compare and jump if equal instruction. CyXCH A,operand: Exchange （swap） the accumulator and the operand. Opcode C4 is not used. DyDJNZoperand,offset: Decrement the operand, and branch to PC+offsetif

21、the result is non-zero. Opcodes D4, D6, and D7 are not used. EyMOV A,operand: Move operand to the accumulator. Opcode E4 is not used. （Use opcode 74 instead.） Fyoperand,A: Move accumulator to the operand. Opcode F4 is not used.Only the ADD, ADDC and SUBB instructions set PSW flags. The INC, DEC, and

22、 logical instructions do not. The CJNE instructions modify the C bit only, to the borrow that results fromoperand1operand2.The 32 opcodes 0x000x3F, plus the few opcodes not used in the above range, are used for other instructions with more limited operand-specification capabilities.One of the reason

23、s for the 8051s popularity is its range of operations on single bits. Bits are always specified by absolute addresses; there is no register-indirect or indexed addressing. Instructions that operate on single bits are: SETBbit, CLRbit, CPLbit: Set, clear, or complement the specified bit JBbit,offset:

24、 Jump if bit set JNB Jump if bit clear JBC Jump if bit set, and clear bit MOV C,bit, MOVbit,C: Move the specified bit to the carry bit, or vice-versa ORL C,bit, ORL C,/bit: OR the bit （or its complement） to the carry bit ANL C,bit, ANL C,/bit: AND the bit （or its complement） to the carry bit XRL C,bit, XRL C,/bit: Exclusive-OR the bit （or its complement） to the carry bitAlthough most instructions require that one operand is the accumulator or an immediate constant, it is possible to perform a MOV directly between two internal RAM locations.