计算机原理与接口技术Word文件下载.docx
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(predictable,thoughnotnecessarilyfast)responsetoeventsintheembeddedsystemtheyarecontrolling.Whencertaineventsoccur,an
interrupt
systemcansignaltheprocessortosuspendprocessingthecurrentinstructionsequenceandtobeginan
interruptserviceroutine
(ISR,or"
interrupthandler"
).TheISRwillperformanyprocessingrequiredbasedonthesourceoftheinterrupt,beforereturningtotheoriginalinstructionsequence.Possibleinterruptsourcesaredevicedependent,andoftenincludeeventssuchasaninternaltimeroverflow,completingananalogtodigitalconversion,alogiclevelchangeonaninputsuchasfromabuttonbeingpressed,anddatareceivedonacommunicationlink.Wherepowerconsumptionisimportantasinbatteryoperateddevices,interruptsmayalsowakeamicrocontrollerfromalowpowersleepstatewheretheprocessorishalteduntilrequiredtodosomethingbyaperipheralevent.
MCS8051
The8051architectureprovidesmanyfunctions(CPU,
RAM,
ROM,
I/O,
logic,
timer,etc.)inasingle
package
∙8-bit
ALU
and
Accumulator,8-bit
Registers
(one
16-bit
registerwithspecial
moveinstructions),8-bit
databus
and2x16-bit
addressbus/programcounter/datapointer
andrelated8/11/16-bitoperations;
henceitismainlyan
8-bitmicrocontroller
∙Boolean
processorwith17instructions,1-bitaccumulator,32registers(4bitaddressable8-bit)andupto144special1-bitaddressableRAMvariables(18bitaddressable8-bit)[3]
∙Multiply,divideand
compare
instructions
∙4fast
switchableregisterbanks
with8registerseach(memorymapped)
∙Fastinterruptwithoptionalregisterbankswitching
∙Interrupts
threads
withselectablepriority[4]
∙Dual16-bit
addressbus
–Itcanaccess2x216
memorylocations–64
kB
(65536locations)eachofRAMandROM
∙128
bytes
ofon-chipRAM(IRAM)
∙4
KiB
ofon-chipROM,witha16-bit(64KiB)addressspace(PMEM).Notincludedon803Xvariants
∙Four8-bit
bi-directional
port
∙UART(serialport)
∙Two16-bitCounter/timers
∙Powersaving
mode(onsomederivatives)
Theonlyregisteronan8051thatisnotmemory-mappedisthe16-bitprogramcounterPC.Thisspecifiestheaddressofthenextinstructiontoexecute.Relativebranchinstructionssupplyan8-bitsignedoffsetwhichisaddedtothePC.
Thefollowingregistersarememory-mappedintothespecialfunctionregisterspace:
∙(0x81)StackpointerSP.Thisisan8-bitregisterusedbysubroutinecallandreturninstructions.Thestackgrowsupward;
theSPisincrementedbeforepushing,anddecrementedafterpoppingavalue.
∙(0x82–83)DatapointerDP.Thisisa16-bitregisterthatisusedforaccessingPMEMandXRAM.
∙(0xD0)ProgramstatuswordPSW.Thiscontainsimportantstatusflags:
∙PSW.0:
PParity.Givestheparity(modulo-2sumofthebitsof)themostrecentALUresult.
∙PSW.1:
UDUserDefined.Forgeneralsoftwareuse,nototherwiseusedbyhardware.
∙PSW.2:
OV
Overflowflag.Setwhenadditionproducesasignedoverflow.
∙PSW.3:
RS0Registerselect0.Thelow-orderbitoftheregisterbank.Setwhenbanksat0x08or0x18areinuse.
∙PSW.4:
RS1Registerselect1.Thehigh-orderbitoftheregisterbank.Setwhenbanksat0x10or0x18areinuse.
∙PSW.5:
F0Flag0.Forgeneralsoftwareuse,nototherwiseusedbyhardware.
∙PSW.6:
AC
auxiliarycarry.Setwhenadditionproducesacarryfrombit3tobit4.
∙PSW.7:
C
Carrybit.
∙(0xE0)AccumulatorA.Thisregisterisusedbymostinstructions.
∙(0xF0)Bregister.Thisisusedasanextensiontotheaccumulatorformultiplyanddivideinstructions.
Inaddition,thereare8generalpurposeregistersR0–R7,mappedtoIRAMbetween0x00and0x1F.Only8bytesofthatrangeareusedatanygiventime,determinedbythebankselectbitsinthePSW.
256singlebitsaredirectlyaddressable.Thesearethe16IRAMlocationsfrom0x20–0x2F,andthe16specialfunctionregisters0x80,0x88,0x90,…,0xF8.
NotethatthePSWdoesnotcontainthecommonN(negative)andZ(zero)flags.Instead,becausetheaccumulatorisabit-addressibleSFR,itispossibletobranchonindividualbitsofit,includingthemsbit.Thereisalsoaninstructiontojumpiftheaccumulatoriszeroornon-zero.
Instructionsareall1to3byteslong,consistingofaninitialopcodebyte,followedbyupto2bytesofoperands.
Thereare16basicALUinstructionsthatoperatebetweentheaccumulatorandasecondoperand,specifiedusingoneofthefollowingaddressingmodes:
∙Registerdirect,R0–R7(opcodes
x8–xF)
∙Registerindirect,@R0or@R1(opcodes
x6and
x7)
∙Memorydirect,specifyinganIRAMorSFRlocation(opcodes
x5,followedby1byteofaddress)
∙Immediate,specifyingan8-bitconstant(opcodes
x4,followedby1byteofdata)
Theinstructionsareasfollows.Notallsupportalladdressingmodes;
theimmediatemodeinparticularissometimesnonsensical:
∙0y
INC
operand:
Incrementthespecifiedoperand.Opcode04specifies"
INCA"
∙1y
DEC
Decrementthespecifiedoperand.Opcode14specifies"
DECA"
∙2y
ADDA,operand:
AddtheoperandtotheaccumulatorA.
∙3y
ADDCA,operand:
Addtheoperand,plustheCbit,totheaccumulator.
∙4y
ORLA,operand:
LogicalORtheoperandintotheAregister.
∙5y
ANLA,operand:
LogicalANDtheoperandintotheAregister.
∙6y
XRLA,operand:
Logicalexclusive-ORtheoperandintotheAregister.
∙7y
MOV
operand,#data:
Moveimmediatedatatotheoperand.Opcode74specifies"
MOVA,#data.
∙8y
address,operand:
MovedatatoanIRAMorSFRregister.
∙9y
SUBBA,operand:
Subtracttheoperandfromtheaccumulator,withborrow.Notethereisnosubtract
without
borrow.
∙Ay
operand,address:
MovedatafromanIRAMorSFRregister.OpcodesA4andA5arenotused.
∙By
CJNE
operand,#data,offset:
Compare
operand
totheimmediate
data,andbranchtoPC+address
ifnotequal.OpcodesB4andB5performCJNEA,operand,offset,formemorydirectandimmediateoperands.Notethereisno"
compareandjumpifequal"
instruction.
∙Cy
XCHA,operand:
Exchange(swap)theaccumulatorandtheoperand.OpcodeC4isnotused.
∙Dy
DJNZ
operand,offset:
Decrementtheoperand,andbranchtoPC+offset
iftheresultisnon-zero.OpcodesD4,D6,andD7arenotused.
∙Ey
MOVA,operand:
Moveoperandtotheaccumulator.OpcodeE4isnotused.(Useopcode74instead.)
∙Fy
operand,A:
Moveaccumulatortotheoperand.OpcodeF4isnotused.
OnlytheADD,ADDCandSUBBinstructionssetPSWflags.TheINC,DEC,andlogicalinstructionsdonot.TheCJNEinstructionsmodifytheCbitonly,totheborrowthatresultsfrom
operand1−operand2.
The32opcodes0x00–0x3F,plusthefewopcodesnotusedintheaboverange,areusedforotherinstructionswithmorelimitedoperand-specificationcapabilities.
Oneofthereasonsforthe8051'
spopularityisitsrangeofoperationsonsinglebits.Bitsarealwaysspecifiedbyabsoluteaddresses;
thereisnoregister-indirectorindexedaddressing.Instructionsthatoperateonsinglebitsare:
∙SETB
bit,CLR
bit,CPL
bit:
Set,clear,orcomplementthespecifiedbit
∙JB
bit,offset:
Jumpifbitset
∙JNB
Jumpifbitclear
∙JBC
Jumpifbitset,andclearbit
∙MOVC,bit,MOV
bit,C:
Movethespecifiedbittothecarrybit,orvice-versa
∙ORLC,bit,ORLC,/bit:
ORthebit(oritscomplement)tothecarrybit
∙ANLC,bit,ANLC,/bit:
ANDthebit(oritscomplement)tothecarrybit
∙XRLC,bit,XRLC,/bit:
Exclusive-ORthebit(oritscomplement)tothecarrybit
Althoughmostinstructionsrequirethatoneoperandistheaccumulatororanimmediateconstant,itispossibletoperformaMOVdirectlybetweentwointernalRAMlocations.