TMS320C6678硬件设计说明英文版.docx

1、TMS320C6678硬件设计说明英文版Product Name: FMC6678Product ID:Project ID:IISC-6678 Board Hardware Design ManualAcronymsTermsDefinitionDDR3 Double Data Rate 3 Interface DSPDigital Signal Processor EEPROM Electrically Erasable Programmable Read Only Memory EMIF External Memory Interface FPGA Field Programmable

2、Gate Array RFUReserved for Future UseI2C Inter Integrated Circuit JTAG Joint Test Action GroupLED Light Emitting Diode PCIE PCI express SDRAM Synchronous Dynamic Random Access Memory SERDES Serializer-Deserializer SGMII Serial Gigabit Media Independent Interface SRIO Serial RapidIO UARTUniversal Asy

3、nchronous Receiver/Transmitter China Research Development Center for Internet of ThingsInstitute of Microelectronics, Chinese Academy of SciencesInformation Identification & System Control Research Center2014-5-8Table of Contents1. OverviewThis chapter provides an overview of the IISC-6678 along wit

4、h the key features and block diagram. 1.1 Key Features 1.2 Functional Overview 1.3 Basic Operation 1.4 Configuration Switch Settings 1.5 Power Supply 1.1 Key FeaturesThe IISC-6678 Board is a high performance, cost-efficient, standalone development platform that enables users to evaluate and develop

5、applications for the Texas Instruments TMS320C6678 Digital Signal Processor (DSP). The IISC-6678 Board also serves as a hardware reference design platform for the TMS320C6678 DSP. Schematics, code examples and application notes are available to ease the hardware development process and to reduce the

6、 time to market. The key features of the IISC-6678 Board are: Texas Instruments multi-core DSP TMS320C6678 512 Mbytes of DDR3-1333 Memory 64 Mbytes of NAND Flash 16MB SPI NOR FLASH Two Gigabit Ethernet ports supporting 10/100/1000 Mbps data-rate and one RJ45/RS232 160 pin LPC FMC Interface containin

7、g SRIO, PCIe, LVDS and Power Supply High Performance connector for HyperLink connector 128K-byte I2C EEPROM for booting User LEDs, 5 Banks of DIP Switches and 4 Software-controlled LEDs TI 60-Pin JTAG header to support all external emulator types Powered by DC power-brick adapter (5V/8.0A)1.2 Functi

8、onal OverviewThe TMS320C66x DSPs (including the TMS320C6678 device) are the highest-performance fixed / floating-point DSP generation in the TMS320C6000 DSP platform. The TMS320C6678device is based on the third-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architec

9、ture developed by Texas Instruments (TI), designed specifically for high density wireline / wireless media gateway infrastructure. It is an ideal solution for IP border gateways, video transcoding and translation, video-server and intelligent voice and video recognition applications. The C66x device

10、s are backward code-compatible from previous devices that are part of the C6000 DSP platform.The functional block diagram of IISC-6678 Board is shown in the figure below:Figure 1.1 Block Diagram of IISC-6678 Board1.3 Basic OperationThe IISC-6678 platform is designed to work with TIs Code Composer St

11、udio (CCS) development environment and ships with a version specifically tailored for this board. CCS can interface with the board through an external emulator.To start operating the board, follow instructions in the Quick Start Guide，to install all the necessary development tools, drivers and docum

12、entation. After the installation has completed, follow the steps below to run Code Composer Studio. 1. Connect USB cable from host PC to IISC-6678 Board. 2. Power-on the board using the power brick adapter (5V/8.0A) supplied along with this IISC-6678 Board.3. Launch Code Composer Studio from host PC

13、 by double clicking on its icon on the PC desktop. Figure 1.2 IISC-6678 Board Layout1.4 Boot Mode and Boot Configuration Switch SettingThe IISC-6678 Board has 20 sliding DIP switches (Board Ref. SW2 to SW6) to determine boot mode, boot configuration, device number, Endian mode, CorePac PLL clock sel

14、ection and PCIe Mode selection options latched at reset by the DSP.1.5 Power SupplyThe IISC-6678 Board can be powered from a single +5V / 8.0A DC (40W) external power supply connected to the DC power jack (JP1). Internally, +5V input is converted into required voltage levels using local DC-DC conver

15、ters. DSPA_CVDD (+0.90V+1.1V) used for the DSP Core logic VCC1V0 is used for DSP internal memory and HyperLink/SRIO/SGMII/PCIe SERDES termination of DSP VCC1V5 is used for DDR3 buffers of DSP, HyperLink/SRIO/SGMII/PCIe SERDES regulators in DSP and DDR3 DRAM chips VCC1V8 is used for DSP PLLs, DSP LVC

16、MOS I/Os and FPGA I/Os driving the DSP +1.8V is used for FPGA I/Os driving the DSP +2.5V is used for Gigabit Ethernet PHY core +1.2V is used for FPGA core and Gigabit Ethernet PHY core 2. Introduction to the IISC-6678 BoardThis chapter provides an introduction and details of interfaces for the IISC-

17、6678 Board. It contains: 2.1 IISC-6678 Board Boot mode and Boot configuration switch settings 2.2 JTAG - Emulation Overview 2.3 Clock Domains 2.4 I2C boot EEPROM / SPI NOR Flash 2.5 UART2.6 FPGA 2.7 Gigabit Ethernet PHY 2.8 Serial RapidIO (SRIO) Interfaces 2.9 DDR3 External Memory Interfaces 2.10 16

18、-bit Asynchronous External Memory Interface 2.11 HyperLink Interface 2.12 PCIe Interface2.13 FMC Interface 2.1 IISC-6678 Board Boot Mode and Boot Configuration Switch SettingsThe IISC-6678 Board has five configuration DIP switches: SW2, SW3, SW4, SW5 and SW6 that contain 17 individual values latched

19、 when reset is released. This occurs when power is applied the board, after the user presses the FULL_RESET push button. SW2 determines general DSP configuration, little or Big Endian mode and boot device selection. SW3, SW4, SW5 and SW6 determine DSP boot device configuration, CorePac PLL setting a

20、nd PCIe mode selection and enable. Figure 2.1 IISC-6678 Board Boot Mode and Configuration 2.2 JTAG - Emulation OverviewThe TI 60-pin JTAG header (EMU1) is provided for high speed real-time emulation. The TI 60-pin JTAG supports all standard TI DSP emulators. An adapter will be required for use with

21、some emulators. The second way of accessing the DSP is through the DSP_JTAG port. The JTAG interface among the DSP, external emulator and DSP_JTAG connector is shown in the below figure.Figure 2.2 IISC-6678 Board JTAG emulation2.3 Clock DomainsThe IISC-6678 Board incorporates a variety of clocks to

22、the TMS320C6678 as well as other devices which are configured automatically during the power up configuration sequence. The figure below illustrates clocking for the system in the IISC-6678 Board module.Figure 2.3 IISC-6678 Board Clock Domains2.4 I2C Boot EEPROM / SPI NOR FlashThe I2C modules on the

23、 TMS320C6678 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may be used to communicate with other controllers in a system or to implement a user interface. The I2C bus is connected to one EEPROM. The serial peripheral interconnect (SPI) module provides an interface betw

24、een the DSP and other SPI-compliant devices. The primary intent of this interface is to allow for connection to a SPI ROM for boot. The SPI module on TMS320C6678 is supported only in Master mode. The NOR FLASH attached to CS0z on the TMS320C6678 is a NUMONYX N25Q128A21. This NOR FLASH size is 16MB.

25、It can contain demonstration programs such as POST or the OOB demonstration. The CS1z of the SPI is used by the DSP to access registers within the FPGA.Figure 2.4 IISC-6678 Board SPI/EEPROM Connections2.5 UARTThe figure 2.5 illustrates the UART connections on the IISC-6678 Board.Figure 2.5 IISC-6678

26、 Board UART Connections2.6 FPGAThe FPGA (Xilinx XC3S200AN) controls the reset mechanism of the DSP and provides boot mode and boot configuration data through SW2, SW3, SW4, SW5 and SW6. The FPGA also supports 4 user LEDs and 1 user switch through control registers. All FPGA registers are accessible

27、over the SPI interface.The figure below shows the interface between TMS320C6678 DSP and FPGA.Figure 2.6 IISC-6678 Board FPGA Connections2.7 Gigabit Ethernet ConnectionsThe IISC-6678 Board provides connectivity for both SGMII Gigabit Ethernet ports. These are shown in figure below:Figure 2.7 IISC-667

28、8 Board Ethernet RoutingThe Ethernet PHY is connected to DSP EMAC to provide a copper interface and routed to a Gigabit RJ-45 connector.2.8 Serial RapidIO (SRIO) InterfaceThe IISC-6678 Board supports high speed SERDES based Serial RapidIO (SRIO) interface. There are total 4 RapidIO ports available o

29、n TMS320C6678. All SRIO ports are routed to FMC edge connector on board. Below figure shows RapidIO connections between the DSP and FMC edge connector.Figure 2.8 IISC-6678 Board SRIO Port Connections2.9 DDR3 External Memory InterfaceThe TMS320C6678 DDR3 interface connects to five 1Gbit (64Meg x 16)

30、DDR3 1333 devices. This configuration allows the use of both “narrow (16-bit)”, “normal (32-bit)”, and “wide (64-bit)” modes of the DDR3 EMIF. SAMSUNG DDR3 K4B1G1646x-HCH9 SDRAMs (64Mx16; 667MHz) are used on the DDR3 EMIF. The figure 2.9 illustrates the implementation for the DDR3 SDRAM memory.Figur

31、e 2.9 IISC-6678 Board SDRAM2.10 16-bit Asynchronous External Memory Interface (EMIF-16)The TMS320C6678 EMIF-16 interface connects to one 512Mbit (64MB) NAND flash device on the IISC-6678 Board. The EMIF16 module provides an interface between DSP and asynchronous external memories such as NAND and NO

32、R flash. For more information, see the External Memory Interface (EMIF16) for KeyStone Devices User Guide (literature number SPRUGZ3). NUMONYX_NAND512R3A2SZA6ENAND flash (64MB) is used on the EMIF-16. The figure 2.10 illustrates the EMIF-16 connections on the IISC-6678 Board.Figure 2.10 IISC-6678 Board EMIF-16 conn