ARM学习经验UART串口无法正确输出字符Word格式.docx

1、SCU_SYSSTAT_OFS EQU 0x08 ; System Status Register OffsetSCU_PCGR0_OFS EQU 0x14 ; Peripheral Clock Gating Register 0 OffsetSCU_PCGR1_OFS EQU 0x18 ; Peripheral Clock Gating Register 1 OffsetSCU_PRR0_OFS EQU 0x1C ; Peripheral Reset Register 0 OffsetSCU_PRR1_OFS EQU 0x20 ; Peripheral Reset Register 1 Of

2、fsetSCU_SCR0_OFS EQU 0x34 ; System Configuration Register 0 OffsetSCU_PECGR0_OFS EQU 0x2CSCU_PECGR1_OFS EQU 0x30SCU_GPIOOUT0_OFS EQU 0x44SCU_GPIOOUT1_OFS EQU 0x48SCU_GPIOOUT2_OFS EQU 0x4CSCU_GPIOOUT3_OFS EQU 0x50SCU_GPIOOUT4_OFS EQU 0x54SCU_GPIOOUT5_OFS EQU 0x58SCU_GPIOOUT6_OFS EQU 0x5CSCU_GPIOOUT7_

3、OFS EQU 0x60SCU_GPIOIN0_OFS EQU 0x64SCU_GPIOIN1_OFS EQU 0x68SCU_GPIOIN2_OFS EQU 0x6CSCU_GPIOIN3_OFS EQU 0x70SCU_GPIOIN4_OFS EQU 0x74SCU_GPIOIN5_OFS EQU 0x78SCU_GPIOIN6_OFS EQU 0x7CSCU_GPIOIN7_OFS EQU 0x80SCU_GPIOTYPE0_OFS EQU 0x84SCU_GPIOTYPE1_OFS EQU 0x88SCU_GPIOTYPE2_OFS EQU 0x8CSCU_GPIOTYPE3_OFS

4、EQU 0x90SCU_GPIOTYPE4_OFS EQU 0x94SCU_GPIOTYPE5_OFS EQU 0x98SCU_GPIOTYPE6_OFS EQU 0x9CSCU_GPIOTYPE7_OFS EQU 0xA0SCU_GPIOTYPE8_OFS EQU 0xA4SCU_GPIOTYPE9_OFS EQU 0xA8SCU_GPIOEMI_OFS EQU 0xACSCU_WKUPSEL_OFS EQU 0xB0SCU_GPIOANA_OFS EQU 0xBCGPIO3_BASE EQU 0x58009000GPIO_DIR_OFS EQU 0x400GPIO_SEL_OFS EQU

5、0x420UART0_BASE EQU 0x5C004000UART1_BASE EQU 0x5C005000UART_FR_OFS EQU 0x18UART_ILPR_OFS EQU 0x20 UART_IBRD_OFS EQU 0x24 UART_FBRD_OFS EQU 0x28 UART_LCR_OFS EQU 0x2C UART_CR_OFS EQU 0x30 UART_IFLS_OFS EQU 0x34 UART_IMSC_OFS EQU 0x38UART_ICR_OFS EQU 0x44 UART_DMACR_OFS EQU 0x48 ConstantsSYSSTAT_LOCK

6、EQU 0x01 ; PLL Lock Status Flash Memory Interface （FMI） definitions （Flash banks sizes and addresses）FMI_BASE EQU 0x54000000 ; FMI Base Address （non-buffered）FMI_BBSR_OFS EQU 0x00 ; Boot Bank Size RegisterFMI_NBBSR_OFS EQU 0x04 ; Non-boot Bank Size RegisterFMI_BBADR_OFS EQU 0x0C ; Boot Bank Base Add

7、ress RegisterFMI_NBBADR_OFS EQU 0x10 ; Non-boot Bank Base Address RegisterFMI_CR_OFS EQU 0x18 ; Control Register APB Bridge 1 & 2 definitions （Peripherals）APB0_BUF_BASE EQU 0x48001802 ; APB Bridge 0 Buffered Base AddressAPB0_NBUF_BASE EQU 0x58000000 ; APB Bridge 0 Non-buffered Base AddressAPB1_BUF_B

8、ASE EQU 0x4C000000 ; APB Bridge 1 Buffered Base AddressAPB1_NBUF_BASE EQU 0x5C000000 ; APB Bridge 1 Non-buffered Base AddressFMI_CR_Val EQU 0x00000018 ;FMI_BBSR_Val EQU 0x00000004 ;1FMI_BBADR_Val EQU 0x00000000 ;2FMI_NBBSR_Val EQU 0x00000002 ;3FMI_NBBADR_Val EQU 0x00400000 ;4FLASH_CFG_Val EQU 0x0000

9、0000 ;5 STARTUP EQU 1 ;SCU_CLKCNTR_Val EQU 0x00031404 ;SCU_PLLCONF_Val EQU 0x000BC019 ;SCU_SYSSTATUS_Val EQU 0x0000003F ;SCU_PWRMNG_Val EQU 0x00000000 ;SCU_ITCMSK_Val EQU 0x00000001 ;5SCU_PCGR0_Val EQU 0x000000FB ;6SCU_PCGR1_Val EQU 0x01FFCC39 ;7SCU_PRR0_Val EQU 0x00001873 ;8SCU_PRR1_Val EQU 0x00FEC

10、839 ;9SCU_MGR0_Val EQU 0x00000000 ;10SCU_MGR1_Val EQU 0x00000000 ;11SCU_PECGR0_Val EQU 0x00000000 ;12SCU_PECGR1_Val EQU 0x00000000 ;13SCU_SCR0_Val EQU 0x000000B1 ;14SCU_WKUPSEL_Val EQU 0x00000000 ;15SCU_GPIOOUT0_Val EQU 0x00000000 ;SCU_GPIOOUT1_Val EQU 0x00000000 ;SCU_GPIOOUT2_Val EQU 0x00000000 ;SC

11、U_GPIOOUT3_Val EQU 0x00000008 ;SCU_GPIOOUT4_Val EQU 0x00000000 ;SCU_GPIOOUT5_Val EQU 0x0000FFA8 ;SCU_GPIOOUT6_Val EQU 0x00000000 ;SCU_GPIOOUT7_Val EQU 0x0000EAAA ;SCU_GPIOIN0_Val EQU 0x00000000 ;SCU_GPIOIN1_Val EQU 0x00000000 ;SCU_GPIOIN2_Val EQU 0x00000000 ;SCU_GPIOIN3_Val EQU 0x00000001 ;SCU_GPIOI

12、N4_Val EQU 0x00000000 ;SCU_GPIOIN5_Val EQU 0x00000000 ;SCU_GPIOIN6_Val EQU 0x00000000 ;SCU_GPIOIN7_Val EQU 0x00000000 ;SCU_GPIOTYPE0_Val EQU 0x00000000 ;16SCU_GPIOTYPE1_Val EQU 0x00000000 ;17SCU_GPIOTYPE2_Val EQU 0x00000000 ;18SCU_GPIOTYPE3_Val EQU 0x00000000 ;19SCU_GPIOTYPE4_Val EQU 0x00000000 ;20S

13、CU_GPIOTYPE5_Val EQU 0x00000000 ;21SCU_GPIOTYPE6_Val EQU 0x00000000 ;22SCU_GPIOTYPE7_Val EQU 0x00000000 ;23SCU_GPIOTYPE8_Val EQU 0x00000000 ;24SCU_GPIOTYPE9_Val EQU 0x00000000 ;25SCU_GPIOANA_Val EQU 0x00000000 ;26GPIO0_DIR_Val EQU 0X00 ;27GPIO1_DIR_Val EQU 0X00 ;28GPIO2_DIR_Val EQU 0X00 ;29GPIO3_DIR

14、_Val EQU 0X0A ;30GPIO4_DIR_Val EQU 0X00 ;31GPIO5_DIR_Val EQU 0X00 ;32GPIO6_DIR_Val EQU 0X00 ;33GPIO7_DIR_Val EQU 0X00 ;34GPIO0_SEL_Val EQU 0X00 ;35GPIO1_SEL_Val EQU 0X00 ;36GPIO2_SEL_Val EQU 0X00 ;37GPIO3_SEL_Val EQU 0X00 ;38GPIO4_SEL_Val EQU 0X00 ;39GPIO5_SEL_Val EQU 0X00 ;40GPIO6_SEL_Val EQU 0X00

15、;41GPIO7_SEL_Val EQU 0X00 ;42RTC_TR_Val EQU 0x14100930 ;RTC_DTR_Val EQU 0x20110301 ;RTC_ATR_Val EQU 0x00000000 ;RTC_CR_Val EQU 0x00000000 ;RTC_MILR_Val EQU 0x00000000 ;UART0_ILPR_Val EQU 0x0034 ;UART0_IBRD_Val EQU 0x004E ;UART0_FBRD_Val EQU 0x0008 ;UART0_LCR_Val EQU 0x0060 ;UART0_CR_Val EQU 0x0301 ;

16、UART0_IFLS_Val EQU 0x0012 ;UART0_IMSC_Val EQU 0x0030 ;UART0_ICR_Val EQU 0x0010 ;UART0_DMACR_Val EQU 0x0000 ;UART1_ILPR_Val EQU 0x0034 ;UART1_IBRD_Val EQU 0x0138 ;UART1_FBRD_Val EQU 0x0020 ;UART1_LCR_Val EQU 0x0070 ;UART1_CR_Val EQU 0x0301 ;UART1_IFLS_Val EQU 0x0012 ;UART1_IMSC_Val EQU 0x0010 ;UART1_

17、ICR_Val EQU 0x0010 ;UART1_DMACR_Val EQU 0x0000 ;UART2_ILPR_Val EQU 0x000C ;UART2_IBRD_Val EQU 0x004E ;UART2_FBRD_Val EQU 0x0008 ;UART2_LCR_Val EQU 0x0060 ;UART2_CR_Val EQU 0x0301 ;UART2_IFLS_Val EQU 0x0012 ;UART2_IMSC_Val EQU 0x0030 ;UART2_ICR_Val EQU 0x0010 ;UART2_DMACR_Val EQU 0x0000 ;/ System Ctr

18、le0 Setup System Configuration （and SRAM Size）/e0e1 Setup Flash Memory Interface （FMI）/e1e2 Setup Clock/e2e3 Setup Peripheral Rese/e3e4 Setup Library Exception Handlers/e4e5 Setup Controller area network （CAN）/e5e6 Setup External Memory Interface（EMI）/e6e7 Setup Vectored interrupt controller （VIC）/e

19、7e8 Setup Universal asynchronous receiver transmitter （UART）/e8e9 Setup General purpose I/O ports （GPIO）/e9e10 Setup Real time clock （RTC）/e10e11 Setup 16-bit timer （TIM）/e11/hSCR0_SETUP EQU 1 ;FMI_SETUP EQU 1 ;CLOCK_SETUP EQU 1 ;2 P_RESET_SETUP EQU 1 ;LEH_SETUP EQU 0 ;CAN_SETUP EQU 0 ;EMI_SETUP EQU

20、 0 ;VIC_SETUP EQU 0 ;UART_SETUP EQU 1 ;GPIO_SETUP EQU 1 ;RTC_SETUP EQU 0 ;TIM_SETUP EQU 0 ;T_Bit EQU 0x20 PRESERVE8 Area Definition and Entry Point Startup Code must be linked first at Address at which it expects to run. AREA Reset, CODE, READONLY ARM Exception Vectors Mapped to Address 0. Absolute

21、addressing mode must be used. Dummy Handlers are implemented as infinite loops which can be modified.Vectors LDR PC, Reset_Addr LDR PC, Undef_Addr LDR PC, SWI_Addr LDR PC, PAbt_Addr LDR PC, DAbt_Addr NOP ; Reserved Vector LDR PC, IRQ_Addr LDR PC, PC, #-0x0FF0 LDR PC, FIQ_Addr IF LEH_SETUP 0 EXTERN U

22、ndefHandler EXTERN SWIHandler EXTERN PAbtHandler EXTERN DAbtHandler EXTERN IRQHandler EXTERN FIQHandler ENDIFReset_Addr DCD Reset_HandlerUndef_Addr DCD UndefHandlerSWI_Addr DCD SWI_HandlerPAbt_Addr DCD PAbtHandlerDAbt_Addr DCD DAbtHandler DCD 0 ; Reserved Address IRQ_Addr DCD IRQHandlerFIQ_Addr DCD

23、FIQHandler IF LEH_SETUP = 0 IMPORT SWI_Handler ; SWI.sUndefHandler B UndefHandlerSWIHandler B SWIHandlerPAbtHandler B PAbtHandlerDAbtHandler B DAbtHandlerIRQHandler B IRQHandlerFIQHandler B FIQHandler Reset Handler EXPORT Reset_HandlerReset_Handler Wait for OSC stabilization NOP IF SCR0_SETUP = 1 LD

24、R R0, =SCU_BASE LDR R1, =SCU_SCR0_Val STR R1, R0, #SCU_SCR0_OFS ORR R1, #0x00000200 IF FMI_SETUP = 1 LDR R0, =FMI_BASE LDR R1, =FMI_BBSR_Val STR R1, R0, #FMI_BBSR_OFS LDR R1, =FMI_NBBSR_Val STR R1, R0, #FMI_NBBSR_OFS LDR R1, =（FMI_BBADR_Val:SHR:2） STR R1, R0, #FMI_BBADR_OFS LDR R2, =（FMI_NBBADR_Val:

25、 STR R2, R0, #FMI_NBBADR_OFS LDR R3, =FMI_CR_Val STR R3, R0, #FMI_CR_OFS ; Write Write flash configuration command （60h） IF :DEF:BOOT_BANK1 MOV R0, R1, LSL #2 ELSE MOV R0, R2, LSL #2 MOV R1, #0x60 STRH R1, R0, #0Write flash configuration confirm command （03h） LDR R2, =（FLASH_CFG_Val:SHL: ADD R0, R0, R2 MOV R1, #0x03 IF CLOCK_SETUP = 1 LDR R1, =SCU_SYSSTATUS_Val STR R1, R0, #SCU_SYSSTAT_OFS ;Clear flag LDR R1, =0x00020002 STR R1, R0, #SCU_CLKCNTR_OFS ; Select OSC as clk src N