ARM学习经验UART串口无法正确输出字符Word格式.docx
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SCU_SYSSTAT_OFSEQU0x08;
SystemStatusRegisterOffset
SCU_PCGR0_OFSEQU0x14;
PeripheralClockGatingRegister0Offset
SCU_PCGR1_OFSEQU0x18;
PeripheralClockGatingRegister1Offset
SCU_PRR0_OFSEQU0x1C;
PeripheralResetRegister0Offset
SCU_PRR1_OFSEQU0x20;
PeripheralResetRegister1Offset
SCU_SCR0_OFSEQU0x34;
SystemConfigurationRegister0Offset
SCU_PECGR0_OFSEQU0x2C
SCU_PECGR1_OFSEQU0x30
SCU_GPIOOUT0_OFSEQU0x44
SCU_GPIOOUT1_OFSEQU0x48
SCU_GPIOOUT2_OFSEQU0x4C
SCU_GPIOOUT3_OFSEQU0x50
SCU_GPIOOUT4_OFSEQU0x54
SCU_GPIOOUT5_OFSEQU0x58
SCU_GPIOOUT6_OFSEQU0x5C
SCU_GPIOOUT7_OFSEQU0x60
SCU_GPIOIN0_OFSEQU0x64
SCU_GPIOIN1_OFSEQU0x68
SCU_GPIOIN2_OFSEQU0x6C
SCU_GPIOIN3_OFSEQU0x70
SCU_GPIOIN4_OFSEQU0x74
SCU_GPIOIN5_OFSEQU0x78
SCU_GPIOIN6_OFSEQU0x7C
SCU_GPIOIN7_OFSEQU0x80
SCU_GPIOTYPE0_OFSEQU0x84
SCU_GPIOTYPE1_OFSEQU0x88
SCU_GPIOTYPE2_OFSEQU0x8C
SCU_GPIOTYPE3_OFSEQU0x90
SCU_GPIOTYPE4_OFSEQU0x94
SCU_GPIOTYPE5_OFSEQU0x98
SCU_GPIOTYPE6_OFSEQU0x9C
SCU_GPIOTYPE7_OFSEQU0xA0
SCU_GPIOTYPE8_OFSEQU0xA4
SCU_GPIOTYPE9_OFSEQU0xA8
SCU_GPIOEMI_OFSEQU0xAC
SCU_WKUPSEL_OFSEQU0xB0
SCU_GPIOANA_OFSEQU0xBC
GPIO3_BASEEQU0x58009000
GPIO_DIR_OFSEQU0x400
GPIO_SEL_OFSEQU0x420
UART0_BASEEQU0x5C004000
UART1_BASEEQU0x5C005000
UART_FR_OFSEQU0x18
UART_ILPR_OFSEQU0x20
UART_IBRD_OFSEQU0x24
UART_FBRD_OFSEQU0x28
UART_LCR_OFSEQU0x2C
UART_CR_OFSEQU0x30
UART_IFLS_OFSEQU0x34
UART_IMSC_OFSEQU0x38
UART_ICR_OFSEQU0x44
UART_DMACR_OFSEQU0x48
Constants
SYSSTAT_LOCKEQU0x01;
PLLLockStatus
FlashMemoryInterface（FMI）definitions（Flashbankssizesandaddresses）
FMI_BASEEQU0x54000000;
FMIBaseAddress（non-buffered）
FMI_BBSR_OFSEQU0x00;
BootBankSizeRegister
FMI_NBBSR_OFSEQU0x04;
Non-bootBankSizeRegister
FMI_BBADR_OFSEQU0x0C;
BootBankBaseAddressRegister
FMI_NBBADR_OFSEQU0x10;
Non-bootBankBaseAddressRegister
FMI_CR_OFSEQU0x18;
ControlRegister
APBBridge1&
2definitions（Peripherals）
APB0_BUF_BASEEQU0x48001802;
APBBridge0BufferedBaseAddress
APB0_NBUF_BASEEQU0x58000000;
APBBridge0Non-bufferedBaseAddress
APB1_BUF_BASEEQU0x4C000000;
APBBridge1BufferedBaseAddress
APB1_NBUF_BASEEQU0x5C000000;
APBBridge1Non-bufferedBaseAddress
FMI_CR_ValEQU0x00000018;
FMI_BBSR_ValEQU0x00000004;
1
FMI_BBADR_ValEQU0x00000000;
2
FMI_NBBSR_ValEQU0x00000002;
3
FMI_NBBADR_ValEQU0x00400000;
4
FLASH_CFG_ValEQU0x00000000;
5
STARTUPEQU1;
SCU_CLKCNTR_ValEQU0x00031404;
SCU_PLLCONF_ValEQU0x000BC019;
SCU_SYSSTATUS_ValEQU0x0000003F;
SCU_PWRMNG_ValEQU0x00000000;
SCU_ITCMSK_ValEQU0x00000001;
5
SCU_PCGR0_ValEQU0x000000FB;
6
SCU_PCGR1_ValEQU0x01FFCC39;
7
SCU_PRR0_ValEQU0x00001873;
8
SCU_PRR1_ValEQU0x00FEC839;
9
SCU_MGR0_ValEQU0x00000000;
10
SCU_MGR1_ValEQU0x00000000;
11
SCU_PECGR0_ValEQU0x00000000;
12
SCU_PECGR1_ValEQU0x00000000;
13
SCU_SCR0_ValEQU0x000000B1;
14
SCU_WKUPSEL_ValEQU0x00000000;
15
SCU_GPIOOUT0_ValEQU0x00000000;
SCU_GPIOOUT1_ValEQU0x00000000;
SCU_GPIOOUT2_ValEQU0x00000000;
SCU_GPIOOUT3_ValEQU0x00000008;
SCU_GPIOOUT4_ValEQU0x00000000;
SCU_GPIOOUT5_ValEQU0x0000FFA8;
SCU_GPIOOUT6_ValEQU0x00000000;
SCU_GPIOOUT7_ValEQU0x0000EAAA;
SCU_GPIOIN0_ValEQU0x00000000;
SCU_GPIOIN1_ValEQU0x00000000;
SCU_GPIOIN2_ValEQU0x00000000;
SCU_GPIOIN3_ValEQU0x00000001;
SCU_GPIOIN4_ValEQU0x00000000;
SCU_GPIOIN5_ValEQU0x00000000;
SCU_GPIOIN6_ValEQU0x00000000;
SCU_GPIOIN7_ValEQU0x00000000;
SCU_GPIOTYPE0_ValEQU0x00000000;
16
SCU_GPIOTYPE1_ValEQU0x00000000;
17
SCU_GPIOTYPE2_ValEQU0x00000000;
18
SCU_GPIOTYPE3_ValEQU0x00000000;
19
SCU_GPIOTYPE4_ValEQU0x00000000;
20
SCU_GPIOTYPE5_ValEQU0x00000000;
21
SCU_GPIOTYPE6_ValEQU0x00000000;
22
SCU_GPIOTYPE7_ValEQU0x00000000;
23
SCU_GPIOTYPE8_ValEQU0x00000000;
24
SCU_GPIOTYPE9_ValEQU0x00000000;
25
SCU_GPIOANA_ValEQU0x00000000;
26
GPIO0_DIR_ValEQU0X00;
27
GPIO1_DIR_ValEQU0X00;
28
GPIO2_DIR_ValEQU0X00;
29
GPIO3_DIR_ValEQU0X0A;
30
GPIO4_DIR_ValEQU0X00;
31
GPIO5_DIR_ValEQU0X00;
32
GPIO6_DIR_ValEQU0X00;
33
GPIO7_DIR_ValEQU0X00;
34
GPIO0_SEL_ValEQU0X00;
35
GPIO1_SEL_ValEQU0X00;
36
GPIO2_SEL_ValEQU0X00;
37
GPIO3_SEL_ValEQU0X00;
38
GPIO4_SEL_ValEQU0X00;
39
GPIO5_SEL_ValEQU0X00;
40
GPIO6_SEL_ValEQU0X00;
41
GPIO7_SEL_ValEQU0X00;
42
RTC_TR_ValEQU0x14100930;
RTC_DTR_ValEQU0x20110301;
RTC_ATR_ValEQU0x00000000;
RTC_CR_ValEQU0x00000000;
RTC_MILR_ValEQU0x00000000;
UART0_ILPR_ValEQU0x0034;
UART0_IBRD_ValEQU0x004E;
UART0_FBRD_ValEQU0x0008;
UART0_LCR_ValEQU0x0060;
UART0_CR_ValEQU0x0301;
UART0_IFLS_ValEQU0x0012;
UART0_IMSC_ValEQU0x0030;
UART0_ICR_ValEQU0x0010;
UART0_DMACR_ValEQU0x0000;
UART1_ILPR_ValEQU0x0034;
UART1_IBRD_ValEQU0x0138;
UART1_FBRD_ValEQU0x0020;
UART1_LCR_ValEQU0x0070;
UART1_CR_ValEQU0x0301;
UART1_IFLS_ValEQU0x0012;
UART1_IMSC_ValEQU0x0010;
UART1_ICR_ValEQU0x0010;
UART1_DMACR_ValEQU0x0000;
UART2_ILPR_ValEQU0x000C;
UART2_IBRD_ValEQU0x004E;
UART2_FBRD_ValEQU0x0008;
UART2_LCR_ValEQU0x0060;
UART2_CR_ValEQU0x0301;
UART2_IFLS_ValEQU0x0012;
UART2_IMSC_ValEQU0x0030;
UART2_ICR_ValEQU0x0010;
UART2_DMACR_ValEQU0x0000;
//<
h>
SystemCtrl
e0>
SetupSystemConfiguration（andSRAMSize）
/e0>
e1>
SetupFlashMemoryInterface（FMI）
/e1>
e2>
SetupClock
/e2>
e3>
SetupPeripheralRese
/e3>
e4>
SetupLibraryExceptionHandlers
/e4>
e5>
SetupControllerareanetwork（CAN）
/e5>
e6>
SetupExternalMemoryInterface（EMI）
/e6>
e7>
SetupVectoredinterruptcontroller（VIC）
/e7>
e8>
SetupUniversalasynchronousreceivertransmitter（UART）
/e8>
e9>
SetupGeneralpurposeI/Oports（GPIO）
/e9>
e10>
SetupRealtimeclock（RTC）
/e10>
e11>
Setup16-bittimer（TIM）
/e11>
/h>
SCR0_SETUPEQU1;
FMI_SETUPEQU1;
CLOCK_SETUPEQU1;
2
P_RESET_SETUPEQU1;
LEH_SETUPEQU0;
CAN_SETUPEQU0;
EMI_SETUPEQU0;
VIC_SETUPEQU0;
UART_SETUPEQU1;
GPIO_SETUPEQU1;
RTC_SETUPEQU0;
TIM_SETUPEQU0;
T_BitEQU0x20
PRESERVE8
AreaDefinitionandEntryPoint
StartupCodemustbelinkedfirstatAddressatwhichitexpectstorun.
AREAReset,CODE,READONLY
ARM
ExceptionVectors
MappedtoAddress0.
Absoluteaddressingmodemustbeused.
DummyHandlersareimplementedasinfiniteloopswhichcanbemodified.
VectorsLDRPC,Reset_Addr
LDRPC,Undef_Addr
LDRPC,SWI_Addr
LDRPC,PAbt_Addr
LDRPC,DAbt_Addr
NOP;
ReservedVector
LDRPC,IRQ_Addr
LDRPC,[PC,#-0x0FF0]
LDRPC,FIQ_Addr
IFLEH_SETUP<
>
0
EXTERNUndefHandler
EXTERNSWIHandler
EXTERNPAbtHandler
EXTERNDAbtHandler
EXTERNIRQHandler
EXTERNFIQHandler
ENDIF
Reset_AddrDCDReset_Handler
Undef_AddrDCDUndefHandler
SWI_AddrDCDSWI_Handler
PAbt_AddrDCDPAbtHandler
DAbt_AddrDCDDAbtHandler
DCD0;
ReservedAddress
IRQ_AddrDCDIRQHandler
FIQ_AddrDCDFIQHandler
IFLEH_SETUP=0
IMPORTSWI_Handler;
SWI.s
UndefHandlerBUndefHandler
SWIHandlerBSWIHandler
PAbtHandlerBPAbtHandler
DAbtHandlerBDAbtHandler
IRQHandlerBIRQHandler
FIQHandlerBFIQHandler
ResetHandler
EXPORTReset_Handler
Reset_Handler
WaitforOSCstabilization
NOP
IFSCR0_SETUP==1
LDRR0,=SCU_BASE
LDRR1,=SCU_SCR0_Val
STRR1,[R0,#SCU_SCR0_OFS]
ORRR1,#0x00000200
IFFMI_SETUP==1
LDRR0,=FMI_BASE
LDRR1,=FMI_BBSR_Val
STRR1,[R0,#FMI_BBSR_OFS]
LDRR1,=FMI_NBBSR_Val
STRR1,[R0,#FMI_NBBSR_OFS]
LDRR1,=（FMI_BBADR_Val:
SHR:
2）
STRR1,[R0,#FMI_BBADR_OFS]
LDRR2,=（FMI_NBBADR_Val:
STRR2,[R0,#FMI_NBBADR_OFS]
LDRR3,=FMI_CR_Val
STRR3,[R0,#FMI_CR_OFS]
;
Write"
Writeflashconfiguration"
command（60h）
IF:
DEF:
BOOT_BANK1
MOVR0,R1,LSL#2
ELSE
MOVR0,R2,LSL#2
MOVR1,#0x60
STRHR1,[R0,#0]
Writeflashconfigurationconfirm"
command（03h）
LDRR2,=（FLASH_CFG_Val:
SHL:
ADDR0,R0,R2
MOVR1,#0x03
IFCLOCK_SETUP==1
LDRR1,=SCU_SYSSTATUS_Val
STRR1,[R0,#SCU_SYSSTAT_OFS];
Clearflag
LDRR1,=0x00020002
STRR1,[R0,#SCU_CLKCNTR_OFS];
SelectOSCasclksrc
N
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