FPGA Based PID Controller Implementation文献翻译Word下载.docx

1、The Islamic University of GazaGaza, PalestineAbstract: Proportional-Integral-Derivative （PID） controllers are widely used in automation systems. They are usually implemented either in hardware using analog components or in software using computer-based systems. They may also be implemented using App

2、lication Specific Integrated Circuits （ASICs）. This paper outlines several modules necessary for building PID controllers on Field Programmable Gate Arrays （FPGAs） which improve speed, accuracy, power, compactness, and cost effectiveness.Two PID controllers for speed and position utilizing these mod

3、ules are implemented and used as experimental platforms to illustrate and test the designed modules.1 IntroductionThere are two approaches for implementing control systems using digital technology.The first approach is based on software which implies a memory-processor interaction. The memory holds

4、the application program while the processor fetches,decodes, and executes the program instructions. Programmable Logic Controllers （PLCs）, microcontrollers, microprocessors, Digital Signal Processors （DSPs）, and general purpose computers are tools for software implementation.On the other hand, the s

5、econd approach is based on hardware. Early hardware implementation is achieved by magnetic relays extensively used in old industry automation systems. It then became achievable by means of digital logic gates and Medium Scale Integration （MSI） components. When the system size and complexity increase

6、s, Application Specific Integrated Circuits （ASICs） are utilized. The ASIC must be fabricated on a manufacturing line, a process that takes several months, before it can be used or even tested . FPGAs are configurable ICs and used to implement logic functions. Early generations of FPGAs were most of

7、ten used as glue logic which is the logic needed to connect the major components of a system. They were often used in prototypes because they could be programmed and inserted into a board in a few minutes, but they did not always make it into the final product. Todays high-end FPGAs can hold several

8、 millions gates and have some significant advantages over ASICs. They ensure ease of design, lower development costs, more product revenue, and the opportunity to speed products to market. At the same time they are superior to software-based controllers as they are more compact, power-efficient, whi

9、le adding high speed capabilities .The target FPGA device used in this research is Spartan-3 manufactured recently by Xilinx . Design development and debugging is carried on a low-cost, full featured kit provided by Digilent . This board, which costs less than a 100$,provides all the tools required

10、to quickly begin designing and verifying Spartan-3 platform designs. While the implemented modules are also suited to other high density FPGAs, designs are based on 50 MHz clock and should be updated if different frequency is used.In control systems, the majority of actuating signals and sensor retu

11、rns are analog signals. Therefore, analog to digital and digital to analog conversion plays an important role in digital controllers. These converters are located at the boundary of the digital controller. Usually there are some modules within the digital system that facilitate communication with th

12、ese converters. In addition, digital controllers usually encompass input/output （I/O） modules to communicate with users. Pushbuttons and seven segment displays are well suited to small size and compact controllers.Along with these four mentioned building blocks a pulse width modulation （PWM） device

13、and an optical encoder interface adapter will be designed. They are used as building blocks in many control applications such as speed and position control. One more building block for digital filters will be addressed in this work.It is essential to implement transfer functions in PID controllers.T

14、he rest of this paper is organized as follows. In Section 2 relevant work is addressed.In Section 3, the building blocks are constructed. In Section 4, experimental work is described. Finally in Section 5, conclusions and suggestions for future work are outlined.2 Relevant workModern FPGAs and their

15、 distinguishable capabilities have been advertised extensively by FPGA vendors. Moreover, some refereed articles addressed the advantages of utilizing these powerful chips . In the past two years, Spartan II and III FPGA families from Xilinx have been successfully utilized in a variety of applicatio

16、ns which include inverters , communications , imbedded processors, and image processing .The implementation of PID controllers using microprocessors and DSP chips is old and well known 1213, whereas very little work can be found in the literature on how to implement PID controllers using FPGAs. The

17、scheme proposed in is based on a distributed arithmetic algorithm where a Look-Up-table （LUT） mechanism inside the FPGA is utilized. The contribution focused on power and area issues while FPGA interfacing is totally unaddressed. In our work we introduce a simple method for implementing PID controll

18、ers together with many related constructing modules. Some other contributions focused on proposing algorithms for tuning the coefficients of PID controllers using FPGAs while the controller itself is still implemented in software. These contributions are considered complementary to our work as they

19、provide tools for building adaptive PID applications. In two different algorithms for fuzzy PID gain conditioner algorithm are proposed. Both are based on fuzzy control that tunes the PID controller on-line.A PWM generator is introduced in . However, only simulation results are presented and the pro

20、posed algorithm results in greater consumption of FPGA resources compared to our algorithm which is tested experimentally. However, despite its complexity, the algorithm in is superior in terms of harmonic content and is more suited to inverter applications.In the authors describe the architecture o

21、f a data acquisition system for a gamma-ray imaging camera. The system has been designed by using Xilinx SpartanII devices and 12-bit parallel A/D converters. In our work, data acquisition for the PID controller, which is implemented using Xilinx Spartan III, is based on 8-bit serial A/D converters.

22、 Similar converters are utilized in 19 to implement an adaptable strain gage conditioner using FPGAs. While being a smart data acquisition approach, it is costly as it is based on a soft intellectual property （IP） processor.3 PID building blocksIn this section, implementation of analog input interfa

23、ce, analog output interface,pulse width modulation, optical encoder interface, user interface, and digital filters are introduced. These building blocks are the major blocks that are essential for implementing most PID controllers on FPGAs.3.1 Analog input interfaceFPGAs are well suited for serial A

24、nalog to Digital （A/D） converters. This is mainly serial interface consumes less communication lines while the FPGA is fast enough to accommodate the high speed serial data. The AD7823 is a high speed,low power, 8-bit A/D converter. The part contains a 4 us typical successive approximation A/D conve

25、rter and a high speed serial interface that interfaces easily to FPGAs as illustrated in Figure 1a.Figure 1. A/D converter interface and timing diagramThe A/D interface adapter （ADIA） is implemented within the FPGA. Inside the FPGA, this adapter facilitates parallel data acquisition. Sampling is ini

26、tiated at the rising edge of a clock applied at the line sample. Once conversion and transmission is completed, a pulse is generated at the interrupt line （int ） and the parallel data will be available at the Data Bus （DB）. The timing diagram of the communication protocol is illustrated in Figure 1b

27、. The whole conversion and acquisition period is 5.4us allowing sampling up to a rate of 185 Kilo Sample per second. This rate is more than sufficient for most PID control applications.3.2 Analog output interfaceThe AD7303 is a dual, 8-bit voltage out Digital to Analog （D/A） converter.This devive us

28、es a verstile 3-wire serial interface that operates at a clock up to 30MHz. The serial input register is 16 bits wide; 8 bits act as data bits for the D/A converter, and the remaining 8 bits make up a control register. It is interfaced to an FPGA as illustrated in Figure 2a.Figure 2. D/A converter i

29、nterface and timing diagram.The D/A interface adapter （DAIA）, which is implemented within the FPGA, facilitates parallel data input for the dual D/A converters. A logic zero on the synchronization signal （SYNC） enables the shift register at the D/A chip to receive data from the DAIAs serial data out

30、put （Sout ）. Its serial clock （SCLK） frequency is 25MHz which is half of the master clock （CLK50） frequency. Data is clocked into the shift register on the rising edge of the serial clock and it is sent most significant bit （MSB） first. Each transfer must consist of a 16-bit packet which is describe

31、d in Table 1 while the timing diagram of the communication protocol is illustrated in Figure 2b. The transmission period of a sample is 680 ns allowing D/A conversion at an excellent rate of 1.47 MHz.3.3 Pulse width modulationSwitching power converters are used in most DC motor drives to deliver the

32、 required energy to the motor. The energy that a switching power converter delivers to a DC motor is controlled by Pulse Width Modulated （PWM） signal applied to the gate of a power transistor. PWM signals are pulse trains with fixed frequency and magnitude and variable pulse width. There is one pulse of fixed magnitude in every Pulse Width Modulation （PWM） period. However, the width of the pulses （duty cycle） changes from pulse to pulse according to a modulating signal as illustrated in Figure 3a.Table 1. Description of the