StratixVGXGSESchematicReviewWorksheetWord下载.docx

1、When using the I/O Analysis tool you must ensure there are no errors with your pinout. Additionally, you should check all warning and critical warning messages to evaluate their impact on your design. You can right click your mouse over any warning or critical warning message and select “Help”. This

2、 will bring open a new Help window with further information on the cause of the warning, and the action that is required.For example, the following warning is generated when a PLL is driven by a global network where the source is a valid dedicated clock input pin, but the pin is not one dedicated to

3、 the particular PLL:Warning: PLL input clock inclk0 is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input Info: Input port INCLK0 of node is driven by clockclkctrl which is OUTCLK output port of Clock Control Block type node clockclkctrlThe help

4、file provides the following:CAUSE:The specified PLLs input clock is not driven by a dedicated input pin. As a result, the input clock delay will not be fully compensated by the PLL. Additionally, jitter performance depends on the switching rate of other design elements. This can also occur if a glob

5、al signal assignment is applied to the clock input pin, which forces the clock to use the non-dedicated global clock network.ACTION:If you want compensation of the specified input clock or better jitter performance, connect the input clock only to an input pin, or assign the input pin only to a dedi

6、cated input clock location for the PLL. If you do not want compensation of the specified input clock, then set the PLL to No Compensation mode.When assigning the input pin to the proper dedicated clock pin location, refer to Clock Networks and PLLs in Stratix V Devices （PDF） for the proper port mapp

7、ing of dedicated clock input pins to PLLs.There are many reports available for use after a successful compilation or I/O analysis. For example, you can use the “All Package Pins” and “I/O Bank Usage” reports within the Compilation Fitter Resource Section to see all of the I/O standards and I/O confi

8、gurable options that are assigned to all of the pins in your design, as well as view the required VCCIO for each I/O bank. These reports must match your schematic pin connections.The review table has the following heading:Plane/SignalSchematic NameConnection GuidelinesComments / IssuesThe first colu

9、mn （Plane/Signal） lists the FPGA voltage or signal pin name. You should only edit this column to remove dedicated or dual purpose pin names that are not available for your device density and package option.The second column （Schematic Name） is for you to enter your schematic name（s） for the signal（s

10、） or plane connected to the FPGA pin（s）.The third column （Connection Guidelines） should be considered “read only” as this contains Alteras recommended connection guidelines for the voltage plane or signal. The fourth column （Comments/Issues） is an area provided as a “notepad” for you to comment on a

11、ny deviations from the connection guidelines, and to verify guidelines are met. In many cases there are notes that provide further information and detail that compliment the connection guidelines.Here is an example of how the worksheet can be used:Plane / Signal name provided by AlteraVCCuser entere

12、d text+0.85VDevice Specific Guidelines provided by AlteraConnected to +0.85V plane, no isolation is necessary. Missing low and medium range decoupling, check PDN.See Notes （1-1） （1-2）.Legal Note: PLEASE REVIEW THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE USING THIS SCHEMATIC REVIEW WORKSHEET

13、（“WORKSHEET”） PROVIDED TO YOU. BY USING THIS WORKSHEET, YOU INDICATE YOUR ACCEPTANCE OF SUCH TERMS AND CONDITIONS, WHICH CONSTITUTE THE LICENSE AGREEMENT （AGREEMENT） BETWEEN YOU AND ALTERA CORPORATION OR ITS APPLICABLE SUBSIDIARIES （ALTERA）.1. Subject to the terms and conditions of this Agreement, A

14、ltera grants to you, for no additional fee, a non-exclusive and non-transferable right to use this Worksheet for the sole purpose of verifying the validity of the pin connections of an Altera programmable logic device-based design. You may not use this Worksheet for any other purpose. There are no i

15、mplied licenses granted under this Agreement, and all rights, except for those granted under this Agreement, remain with Altera.2. Altera does not guarantee or imply the reliability, or serviceability, of this Worksheet or other items provided as part of this Worksheet. This Worksheet is provided AS

16、 IS. ALTERA DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. ALTERA HAS NO OBLIGATION TO PROVIDE YOU WITH ANY SUPPORT OR MAINTENANCE.3. In no event shall the aggregate liability of Altera relati

17、ng to this Agreement or the subject matter hereof under any legal theory （whether in tort, contract, or otherwise）, exceed One Hundred USDollars （US$100.00）. In no event shall Altera be liable for any lost revenue, lost profits, or other consequential, indirect, or special damages caused by your use

18、 of this Worksheet even if advised of the possibility of such damages.4. This Agreement may be terminated by either party for any reason at any time upon 30-days prior written notice. This Agreement shall be governed by the laws of the State of California, without regard to conflict of law or choice

19、 of law principles. You agree to submit to the exclusive jurisdiction of the courts in the County of Santa Clara, State of California for the resolution of any dispute or claim arising out of or relating to this Agreement. The parties hereby agree that the party who is not the substantially prevaili

20、ng party with respect to a dispute, claim, or controversy relating to this Agreement shall pay the costs actually incurred by the substantially prevailing party in relation to such dispute, claim, or controversy, including attorneys fees. Failure to enforce any term or condition of this Agreement sh

21、all not be deemed a waiver of the right to later enforce such term or condition or any other term or condition of the Agreement. BY USING THIS WORKSHEET, YOU ACKNOWLEDGE THAT YOU HAVE READ THIS AGREEMENT, UNDERSTAND IT, AND AGREE TO BE BOUND BY ITS TERMS AND CONDITIONS. YOU AND ALTERA FURTHER AGREE

22、THAT IT IS THE COMPLETE AND EXCLUSIVE STATEMENT OF THE AGREEMENT BETWEEN YOU AND ALTERA, WHICH SUPERSEDES ANY PROPOSAL OR PRIOR AGREEMENT, ORAL OR WRITTEN, AND ANY OTHER COMMUNICATIONS BETWEEN YOU AND ALTERA RELATING TO THE SUBJECT MATTER OF THIS AGREEMENT.IndexSection I: Power Section II: Configura

23、tionSection III: TransceiverSection IV: I/O a: Clock Pins b: Dedicated and Dual Purpose Pins c: Dual Purpose Differential I/O pinsSection V: External Memory Interface Pins DDR/2 Interface Pins DDR/2 Termination Guidelines DDR3 Interface Pins d: DDR3 Termination Guidelines e: QDRII/+ Interface pins f

24、: QDRII/+ Termination GuidelinesSection VI: Document Revision History Power Documentation: Stratix V DevicesStratix V Pin Out Files Stratix V E, GS, GX Device Family Pin Connection Guidelines （PDF）Stratix V Early Power EstimatorStratix V Early Power Estimator User Guide （PDF）Power Delivery Network （

25、PDN） Tool For Stratix V DevicesDevice-Specific Power Delivery Network （PDN） Tool User Guide （PDF）PowerPlay Power Analyzer Support ResourcesAltera Board Design Resource Center （General board design guidelines, PDN design, isolation, tools, and more）AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs （PDF）AN 597: Getting Started Flow for Board Designs （PDF）Errata Sheet a