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1、101 Innovation DriveSan Jose,CA HyperTransport MegaCore FunctionUser GuideMegaCore Version:#9.0Document Date:#March 2009Copyright 2009 Altera Corporation.All rights reserved.Altera,The Programmable Solutions Company,the stylized Altera logo,specific device designations,and all otherwords and logos t

2、hat are identified as trademarks and/or service marks are,unless noted otherwise,the trademarks and service marks of Altera Corporation in the U.S.and othercountries.All other product or service names are the property of their respective holders.Altera products are protected under numerous U.S.and f

3、oreign patents and pending ap-plications,maskwork rights,and copyrights.Altera warrants performance of its semiconductor products to current specifications in accordance with Alteras standard warranty,but reserves the right to make changes to any products and services at any time without notice.Alte

4、ra assumes no responsibility or liability arising out of the application or use ofany information,product,or service described herein except as expressly agreed to in writing by Altera Corporation.Altera customers are advised to obtain the latest version ofdevice specifications before relying on any

5、 published information and before placing orders for products or services.UG-MCHYPRTRNS-1.11 March 2009Altera CorporationHyperTransport MegaCore Function User GuideContentsChapter 1.About this MegaCore FunctionRelease Information .11Device Family Support.11Introduction .12Features.12OpenCore Plus Ev

6、aluation .13Performance.13Chapter 2.Getting StartedDesign Flow .21MegaCore Function Walkthrough .22Create a New Quartus II Project.22Launch the MegaWizard Plug-in Manager .23Step 1:#Parameterize.25Step 2:#Set Up Simulation .29Step 3:#Generate .211Simulate the Design .213Compile the Design.213Program

7、 a Device .214Set Up Licensing .215Append the License to Your license.dat File .215Specify the License File in the Quartus II Software.215Example Simulation and Compilation.216Example Quartus II Project.216Example Simulation with Test Vectors.216Chapter 3.SpecificationsHyperTransport Technology Over

8、view.31HT Systems .32HT Flow Control.33HyperTransport MegaCore Function Specification.33Physical Interface .34Synchronization and Alignment .34Protocol Interface .35Clocking Options .37HyperTransport MegaCore Function Parameters and HT Link Performance .310Signals .314CSR Module.331OpenCore Plus Tim

9、e-Out Behavior.340Appendix A.ParametersIntroduction .A1Parameter Lists .A1Device Family and Read Only Registers.A1Base Address Registers .A2Clocking Options .A3Advanced Settings .A3ivContentsHyperTransport MegaCore Function User Guide March 2009Altera CorporationAppendix B.Stratix Device Pin Assignm

10、entsIntroduction .B1Guidelines.B1Appendix C.Example DesignGeneral Description .C1Additional InformationRevision History .Info1How to Contact Altera .Info1Typographic Conventions .Info2 March 2009Altera CorporationHyperTransport MegaCore Function User GuidePreliminary1.About this MegaCore FunctionRel

11、ease InformationTable 11 provides information about this release of the HyperTransport MegaCore function.Altera verifies that the current version of the Quartus II software compiles the previous version of each MegaCore function.Any exceptions to this verification are reported in the MegaCore IP Lib

12、rary Release Notes and Errata.Altera does not verify compilation with MegaCore function versions older than one release.Device Family SupportMegaCore functions provide either full or preliminary support for target Altera device families:#Full support means the MegaCore function meets all functional

13、and timing requirements for the device family and may be used in production designs.Preliminary support means the MegaCore function meets all functional requirements,but may still be undergoing timing analysis for the device family;#it may be used in production designs with caution.Table 12 shows th

14、e level of support offered by the HyperTransport MegaCore function for each of the Altera device families.Table 11.HyperTransport MegaCore Function Release InformationItemDescriptionVersion9.0Release DateMarch 2009Ordering CodeIP-HTProduct ID（s）0098Vendor ID（s）6AF7Table 12.Device Family SupportDevic

15、e FamilySupportHardCopy StratixFullStratixFullStratix IIFullStratix II GXPreliminaryStratix GXFullOther device familiesNo support12Chapter 1:#About this MegaCore FunctionIntroductionHyperTransport MegaCore Function User Guide March 2009Altera CorporationPreliminaryIntroductionThe HyperTransport Mega

16、Core function implements high-speed packet transfers between physical（PHY）and link-layer devices,and is fully compliant with the HyperTransport I/O Link Specification,Revision 1.03.This MegaCore function allows designers to interface to a wide range of HyperTransport technology（HT）enabled devices quickly and easily,including network processors,coprocessors,video chipsets,and ASICs.FeaturesThe HyperTransport MegaCore function has the following features:#8-bit fully integrated HT end-chain interfacePacket-