英语I2C总线规范21部分Word下载.docx

1、JANUARY 200011 EXTENSIONS TO THE STANDARD-MODE I2C-BUS SPECIFICATIONThe Standard-mode I2C-bus specification, with its data transfer rate of up to 100 kbit/s and 7-bit addressing, has been in existence since the beginning of the 1980s. This concept rapidly grew in popularity and is today accepted wor

2、ldwide as a de facto standard with several hundred different compatible ICs on offer from Philips Semiconductors and other suppliers. To meet the demands for higher speeds, as well as make available more slave address for the growing number of new devices, the Standard-mode I2C-bus specification was

3、 upgraded over the years and today is available with the following extensions: Fast-mode, with a bit rate up to 400 kbit/s. High-speed mode （Hs-mode）, with a bit rate up to 3.4 Mbit/s. 10-bit addressing, which allows the use of up to 1024 additional slave addresses.There are two main reasons for ext

4、ending the regular I2C-bus specification: Many of todays applications need to transfer large amounts of serial data and require bit rates far in excess of 100 kbit/s （Standard-mode）, or even 400 kbit/s （Fast-mode）. As a result of continuing improvements in semiconductor technologies, I2C-bus devices

5、 are now available with bit rates of up to 3.4 Mbit/s （Hs-mode） without any noticeable increases in the manufacturingcost of the interface circuitry. As most of the 112 addresses available with the 7-bit addressing scheme were soon allocated, it became apparent that more address combinations were re

6、quired to prevent problems with the allocation of slave addresses for new devices. This problem was resolved with the new 10-bit addressing scheme, which allowed about a tenfold increase in available addresses.New slave devices with a Fast- or Hs-mode I2C-bus interface can have a 7- or a 10-bit slav

7、e address. If possible, a 7-bit address is preferred as it is the cheapest hardware solution and results in the shortest message length. Devices with 7- and 10-bit addresses can be mixed in the same I2C-bus system regardless of whether it is an F/S- or Hs-mode system. Both existing and future master

8、s can generate either 7- or 10-bit addresses.12 FAST-MODEWith the Fast-mode I2C-bus specification, the protocol,format, logic levels and maximum capacitive load for the SDA and SCL lines quoted in the Standard-mode I2C-bus specification are unchanged. New devices with an I2C-bus interface must meet

9、at least the minimum requirements of the Fast- or Hs-mode specification （see Section 13）.Fast-mode devices can receive and transmit at up to 400 kbit/s. The minimum requirement is that they can synchronize with a 400 kbit/s transfer; they can then prolong the LOW period of the SCL signal to slow dow

10、n the transfer. Fast-mode devices are downward-compatible and can communicate with Standard-mode devices in a 0 to 100 kbit/s I2C-bus system. As Standard-mode devices, however, are not upward compatible, they should not be incorporated in a Fast-mode I2C-bus system as they cannot follow the higher t

11、ransfer rate andunpredictable states would occur.The Fast-mode I2C-bus specification has the following additional features compared with the Standard-mode: The maximum bit rate is increased to 400 kbit/s. Timing of the serial data （SDA） and serial clock （SCL） signals has been adapted. There is no ne

12、ed for compatibility with other bus systems such as CBUS because they cannot operate at the increased bit rate. The inputs of Fast-mode devices incorporate spike suppression and a Schmitt trigger at the SDA and SCL inputs. The output buffers of Fast-mode devices incorporate slope control of the fall

13、ing edges of the SDA and SCL signals. If the power supply to a Fast-mode device is switched off, the SDA and SCL I/O pins must be floating so that they dont obstruct the bus lines. The external pull-up devices connected to the bus lines must be adapted to accommodate the shorter maximum permissible

14、rise time for the Fast-mode I2C-bus. For bus loads up to 200 pF, the pull-up device for each bus line can be a resistor; for bus loads between 200 pF and 400 pF, the pull-up device can be a current source （3 mA max.） or a switched resistor circuit （see Fig.43）.13 Hs-MODEHigh-speed mode （Hs-mode） dev

15、ices offer a quantum leap in I2C-bus transfer speeds. Hs-mode devices can transfer information at bit rates of up to 3.4 Mbit/s, yet they remain fully downward compatible with Fast- or Standard-mode （F/S-mode） devices for bi-directional communication in a mixed-speed bus system. With the exception t

16、hat arbitration and clock synchronization is not performed during the Hs-mode transfer, the same serial bus protocol and data format is maintained as with the F/S-mode system. Depending on the application, new devices may have a Fast or Hs-mode I2C-bus interface,although Hs-mode devices are preferred as they can be designed-in to a greater number of applications.13.1 High speed tra