VHDL与数字集成电路设计VHDL3-1PPT文档格式.ppt

1、边沿敏感DClkQClkDQDClkQClkDQ 锁存器类型锁存器类型基于锁存器的设计基于锁存器的设计 N latch is transparentwhen f f=0 P latch is transparent when f f=1NLatchLogicLogicPLatchf f时间约束时间约束tCLKtDtc 2 2 qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ正反馈与双稳态正反馈与双稳态Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1双稳态双稳态Gain should be larger than 1 in the transit

2、ion region基本锁存器电路基本锁存器电路DCLKCLKDConverting into a MUXForcing the state（can implement as NMOS-only）多路选择器锁存器多路选择器锁存器Negative latch（transparent when CLK=0）Positive latch（transparent when CLK=1）CLK10DQ0CLK1DQ具体电路具体电路主从寄存器主从寄存器Two opposite latches trigger on edgeAlso called master-slave latch pair 具体电路具体

3、电路Multiplexer-based latch pair建立时间建立时间降低时钟负载的主从寄存器降低时钟负载的主从寄存器RS触发器触发器带有时钟控制的带有时钟控制的RS触发器触发器Cross-coupled NANDsAdded clock不同的状态储存机制不同的状态储存机制DCLKCLKQDynamic（charge-based）StaticC2MOS寄存器寄存器施密特触发器施密特触发器VTC with hysteresisRestores signal slopes CMOS施密特触发器施密特触发器Moves switching thresholdof the first invert

4、er CMOS施密特触发器施密特触发器2数据寄存器及相关电路数据寄存器及相关电路最快数据传递：时钟周期最快数据传递：时钟周期数据寄存器及相关电路数据寄存器及相关电路最快数据传递时间：时钟周期最快数据传递时间：时钟周期在输入端添加控制电路，构成其他类型的触发器在输入端添加控制电路，构成其他类型的触发器D D触发器的控制与扩展触发器的控制与扩展数据寄存器及相关电路数据寄存器及相关电路数据寄存器及相关电路数据寄存器及相关电路D D触发器的控制与扩展触发器的控制与扩展并行寄存与移位寄存并行寄存与移位寄存数据寄存器及相关电路数据寄存器及相关电路多功能移位寄存器多功能移位寄存器数据寄存器及相关电路数据寄存

5、器及相关电路第四章第四章 算数逻辑单元算数逻辑单元4.1 加法器加法器4.2 乘法器乘法器VHDL与数字集成电路设计与数字集成电路设计加法器设计加法器设计加法运算从最低位开始，逐步向高位进行；加法运算从最低位开始，逐步向高位进行；每一位相加时，产生每一位相加时，产生1 1位结果（位结果（s s），同时产生），同时产生1 1位进位进位（位（c c）；）；最低位相加时，只需要考虑最低位相加时，只需要考虑2 2个数据的相加：半加；个数据的相加：其余位相加时，需要考虑其余位相加时，需要考虑3 3个数据的相加：全加。4.1 加法器、算数逻辑单元加法器、算数逻辑单元加法器设计加法器设计半加器半加器4.1

6、加法器、算数逻辑单元加法器、算数逻辑单元加法器设计加法器设计全加器全加器4.2 加法器、算数逻辑单元加法器、算数逻辑单元利用半加单元设计全加器利用半加单元设计全加器4.2 加法器、算数逻辑单元加法器、算数逻辑单元可扩展的串行加法器：可扩展的串行加法器：采用全加器级联构成采用全加器级联构成4.2 加法器、算数逻辑单元加法器、算数逻辑单元4位串行加法器：位串行加法器：ASIC设计设计 第第1级采用半加；级采用半加；最高级取消进位。4.2 加法器、算数逻辑单元加法器、算数逻辑单元36Full-AdderFull-Adder37The Binary AdderThe Binary Adder38Exp

7、ress Sum and Carry as a function of P,G,DExpress Sum and Carry as a function of P,G,DDefine 3 new variable which ONLY depend on A,BGenerate（G）=ABPropagate（P）=A BDelete=A BCan also derive expressions for S and Co based on D and P Propagate（P）=A+BNote that we will be sometimes using an alternate defin

8、ition for 39The Ripple-Carry AdderThe Ripple-Carry AdderWorst case delay linear with the number of bitsGoal:Make the fastest possible carry path circuittd=O（N）tadder=（N-1）tcarry+tsum40Complimentary Static CMOS Full Complimentary Static CMOS Full AdderAdder28 Transistors41Inversion PropertyInversion

9、Property42Minimize Critical Path by Reducing Inverting Minimize Critical Path by Reducing Inverting StagesStagesExploit Inversion Property43A Better Structure:The Mirror AdderA Better Structure:The Mirror Adder44Transmission Gate Full AdderTransmission Gate Full Adder45Manchester Carry ChainManchest

10、er Carry Chain46Manchester Carry ChainManchester Carry Chain47Carry-Bypass AdderCarry-Bypass AdderAlso called Carry-Skip48Carry-Bypass Adder（cont.）Carry-Bypass Adder（cont.）tadder=tsetup+Mtcarry+（N/M-1）tbypass+（M-1）tcarry+tsum49Carry Ripple versus Carry BypassCarry Ripple versus Carry Bypass50Carry-S

11、elect AdderCarry-Select Adder51Carry Select Adder:Critical Path Carry Select Adder:Critical Path 52Linear Carry Select Linear Carry Select 53Square Root Carry Select Square Root Carry Select 54LookAhead-Basic IdeaLookAhead-Basic Idea 55Look-Ahead:TopologyLook-Ahead:TopologyExpanding Lookahead equati

12、ons:All the way:56Logarithmic Look-Ahead AdderLogarithmic Look-Ahead Adder57Carry Lookahead TreesCarry Lookahead TreesCan continue building the tree hierarchically.58Tree AddersTree Adders16-bit radix-2 Kogge-Stone tree59Example:Domino AdderExample:Domino AdderPropagateGenerate60Example:Domino Adder

13、PropagateGenerate第四章算数逻辑单元第四章算数逻辑单元4.1 加法器加法器4.2 乘法器乘法器VHDL与数字集成电路设计与数字集成电路设计8 8位乘法器设计：基于基本单元的扩展设计位乘法器设计：基于基本单元的扩展设计2 2位乘法器：由位乘法器：由1 1位乘法结果相加而成位乘法结果相加而成成本：成本：4+4+4 4+4+4 门门时间：时间：1+31+34.3 数据累加与乘法器设计数据累加与乘法器设计8 8位乘法器设计：基于基本单元的扩展设计4 4位乘法器：由2 2位乘法结果相加而成位乘法结果相加而成4 4个个2 2位乘法器并行运位乘法器并行运算，产生算，产生4 4组数据，然组数据

14、，然后进行相加。后进行相加。4.3 数据累加与乘法器设计数据累加与乘法器设计65The Binary MultiplicationThe Binary Multiplication66The Array MultiplierThe Array Multiplier67The MxN Array MultiplierThe MxN Array Multiplier Critical Path Critical PathCritical Path 1&268Carry-Save MultiplierCarry-Save Multiplier69Multiplier FloorplanMultipl

15、ier Floorplan70Wallace-Tree MultiplierWallace-Tree Multiplier71Wallace-Tree MultiplierWallace-Tree Multiplier72The Binary ShifterThe Binary Shifter73The Barrel ShifterThe Barrel ShifterArea Dominated by Wiring744x4 barrel shifter4x4 barrel shifterWidthbarrel 2 pm M75Logarithmic ShifterLogarithmic Shifter760-7 bit Logarithmic Shifter0-7 bit Logarithmic ShifterA3A2A1A0Out3Out2Out1Out0